Seungdo An

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Portland, OR, US

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Patents Grantslast 30 patents

Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,652,045
- Issue date May 16, 2023
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via contact patterning method to increase edge placement error margin
- Patent number 11,211,324
- Issue date Dec 28, 2021
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT INTERCONNECT STRUCTURES INCLUDING COPPER-FREE VIAS
- Publication number 20230143021
- Publication date May 11, 2023
- Intel Corporation
- Daniel B. OBrien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
- Publication number 20220051975
- Publication date Feb 17, 2022
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
- Publication number 20210082805
- Publication date Mar 18, 2021
- Intel Corporation
- Mohit K. Haran
- H01 - BASIC ELECTRIC ELEMENTS