Seyhan KARAKULAK

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 11,815,996
- Issue date Nov 14, 2023
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating optimal read levels
- Patent number 11,488,673
- Issue date Nov 1, 2022
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 11,327,837
- Issue date May 10, 2022
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for identifying erased memory areas
- Patent number 10,884,854
- Issue date Jan 5, 2021
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibrating optimal read levels
- Patent number 10,566,061
- Issue date Feb 18, 2020
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for scanning for erased flash memory pages
- Patent number 10,387,246
- Issue date Aug 20, 2019
- Western Digital Technologies, Inc.
- Richard David Barndt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read level grouping algorithms for increased flash performance
- Patent number 9,905,302
- Issue date Feb 27, 2018
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Read level grouping for increased flash performance
- Patent number 9,720,754
- Issue date Aug 1, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Read level grouping algorithms for increased flash performance
- Patent number 9,583,202
- Issue date Feb 28, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibrating optimal read levels
- Patent number 9,576,671
- Issue date Feb 21, 2017
- Western Digital Technologies, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Word-line inter-cell interference detector in flash system
- Patent number 9,343,170
- Issue date May 17, 2016
- HGST Technologies Santa Ana, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Inter-cell interference algorithms for soft decoding of LDPC codes
- Patent number 9,117,529
- Issue date Aug 25, 2015
- HGST Technologies Santa Ana, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE
Information Patent Grant
Word-line inter-cell interference detector in flash system
- Patent number 8,493,791
- Issue date Jul 23, 2013
- Stec, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and System for Identifying Erased Memory Areas
- Publication number 20220214941
- Publication date Jul 7, 2022
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS
- Publication number 20210103496
- Publication date Apr 8, 2021
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Calibrating Optimal Read Levels
- Publication number 20200160920
- Publication date May 21, 2020
- Western Digital Technologies, Inc.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS
- Publication number 20190324853
- Publication date Oct 24, 2019
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SCANNING FOR ERASED FLASH MEMORY PAGES
- Publication number 20180373591
- Publication date Dec 27, 2018
- Western Digital Technologies, Inc.
- Richard David BARNDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALIBRATING OPTIMAL READ LEVELS
- Publication number 20170229186
- Publication date Aug 10, 2017
- WESTERN DIGITAL TECHNOLOGIES, INC.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL GROUPING FOR INCREASED FLASH PERFORMANCE
- Publication number 20160147582
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE
- Publication number 20160148701
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
CALIBRATING OPTIMAL READ LEVELS
- Publication number 20160148702
- Publication date May 26, 2016
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
- Publication number 20150371714
- Publication date Dec 24, 2015
- HGST NETHERLANDS B.V.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
- Publication number 20150364202
- Publication date Dec 17, 2015
- HGST Technologies Santa Ana, Inc.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM
- Publication number 20130163327
- Publication date Jun 27, 2013
- STEC, Inc.
- Seyhan KARAKULAK
- G11 - INFORMATION STORAGE
Information Patent Application
INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES
- Publication number 20130163328
- Publication date Jun 27, 2013
- STEC, Inc.
- Seyhan Karakulak
- G11 - INFORMATION STORAGE

Seyhan KARAKULAK

Person

Patents Grantslast 30 patents

Method and system for identifying erased memory areas

Calibrating optimal read levels

Method and system for identifying erased memory areas

Method and system for identifying erased memory areas

Calibrating optimal read levels

Method and system for scanning for erased flash memory pages

Read level grouping algorithms for increased flash performance

Read level grouping for increased flash performance

Read level grouping algorithms for increased flash performance

Calibrating optimal read levels

Word-line inter-cell interference detector in flash system

Inter-cell interference algorithms for soft decoding of LDPC codes

Word-line inter-cell interference detector in flash system

Patents Applicationslast 30 patents

Method and System for Identifying Erased Memory Areas

METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS

Calibrating Optimal Read Levels

METHOD AND SYSTEM FOR IDENTIFYING ERASED MEMORY AREAS

METHOD AND SYSTEM FOR SCANNING FOR ERASED FLASH MEMORY PAGES

CALIBRATING OPTIMAL READ LEVELS

READ LEVEL GROUPING FOR INCREASED FLASH PERFORMANCE

READ LEVEL GROUPING ALGORITHMS FOR INCREASED FLASH PERFORMANCE

CALIBRATING OPTIMAL READ LEVELS

WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM

INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES

WORD-LINE INTER-CELL INTERFERENCE DETECTOR IN FLASH SYSTEM

INTER-CELL INTERFERENCE ALGORITHMS FOR SOFT DECODING OF LDPC CODES