Shailendra Mishra

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Capacitor top plate over source/drain to form a 1T memory device
- Patent number 8,716,081
- Issue date May 6, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid orientation substrate with stress layer
- Patent number 8,274,115
- Issue date Sep 25, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tunable spacers for improved gapfill
- Patent number 8,236,678
- Issue date Aug 7, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Ramachandramurthy Pradeep Yelehanka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming shallow trench isolation structures for integrate...
- Patent number 8,178,417
- Issue date May 15, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 8,143,651
- Issue date Mar 27, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming source and drain of field-effect-transistor and s...
- Patent number 8,138,053
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Henry K. Utomo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacture of an integrated circuit system with self-ali...
- Patent number 8,053,327
- Issue date Nov 8, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell structure and method for fabrication thereof
- Patent number 7,999,300
- Issue date Aug 16, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Zhao Lun
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit system employing selective epitaxial growth tech...
- Patent number 7,795,680
- Issue date Sep 14, 2010
- Chartered Semiconductor Manufacturing Ltd.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested and isolated transistors with reduced impedance difference
- Patent number 7,767,577
- Issue date Aug 3, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Johnny Widodo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming mask patterns on semiconductor wafers that compe...
- Patent number 7,541,290
- Issue date Jun 2, 2009
- Samsung Electronics Co., Ltd.
- Chong Kwang Chang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20100301424
- Publication date Dec 2, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF
- Publication number 20100187587
- Publication date Jul 29, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Zhao LUN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TUNABLE SPACERS FOR IMPROVED GAPFILL
- Publication number 20100148269
- Publication date Jun 17, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Ramachandramurthy Pradeep YELEHANKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...
- Publication number 20100009527
- Publication date Jan 14, 2010
- Chartered Semiconductor Manufacturing LTD.
- Yong Meng Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...
- Publication number 20090261448
- Publication date Oct 22, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Shailendra MISHRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER
- Publication number 20090236663
- Publication date Sep 24, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE
- Publication number 20090206408
- Publication date Aug 20, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Johnny WIDODO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...
- Publication number 20090146262
- Publication date Jun 11, 2009
- Chartered Semiconductor Manufacturing LTD.
- Huang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE
- Publication number 20080224228
- Publication date Sep 18, 2008
- Lee Wee Teo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming Mask Patterns on Semiconductor Wafers that Compe...
- Publication number 20080220609
- Publication date Sep 11, 2008
- Chong Kwang Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SOURCE AND DRAIN OF FIELD-EFFECT-TRANSISTOR AND S...
- Publication number 20080166847
- Publication date Jul 10, 2008
- International Business Machines Corporation
- Henry K. Utomo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM WITH ISOLATION
- Publication number 20080150074
- Publication date Jun 26, 2008
- Chartered Semiconductor Manufacturing LTD.
- Shailendra Mishra
- H01 - BASIC ELECTRIC ELEMENTS

Shailendra Mishra

Person

Patents Grantslast 30 patents

Capacitor top plate over source/drain to form a 1T memory device

Hybrid orientation substrate with stress layer

Tunable spacers for improved gapfill

Method of forming shallow trench isolation structures for integrate...

Nested and isolated transistors with reduced impedance difference

Method of forming source and drain of field-effect-transistor and s...

Method of manufacture of an integrated circuit system with self-ali...

Memory cell structure and method for fabrication thereof

Integrated circuit system employing selective epitaxial growth tech...

Nested and isolated transistors with reduced impedance difference

Methods of forming mask patterns on semiconductor wafers that compe...

Patents Applicationslast 30 patents

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

MEMORY CELL STRUCTURE AND METHOD FOR FABRICATION THEREOF

TUNABLE SPACERS FOR IMPROVED GAPFILL

INTEGRATED CIRCUIT SYSTEM EMPLOYING SINGLE MASK LAYER TECHNIQUE FOR...

METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURES FOR INTEGRATE...

HYBRID ORIENTATION SUBSTRATE WITH STRESS LAYER

NESTED AND ISOLATED TRANSISTORS WITH REDUCED IMPEDANCE DIFFERENCE

INTEGRATED CIRCUIT SYSTEM EMPLOYING SELECTIVE EPITAXIAL GROWTH TECH...

CAPACITOR TOP PLATE OVER SOURCE/DRAIN TO FORM A 1T MEMORY DEVICE

Methods of Forming Mask Patterns on Semiconductor Wafers that Compe...

METHOD OF FORMING SOURCE AND DRAIN OF FIELD-EFFECT-TRANSISTOR AND S...

INTEGRATED CIRCUIT SYSTEM WITH ISOLATION