Shailesh Shah

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Folsom, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 11,620,256
- Issue date Apr 4, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic error handling using parity and redundant rows
- Patent number 9,075,741
- Issue date Jul 7, 2015
- Intel Corporation
- Altug Koker
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220261347
- Publication date Aug 18, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220179787
- Publication date Jun 9, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic optimal integrated circuit generator from algorithms and...
- Publication number 20130346926
- Publication date Dec 26, 2013
- ALGOTOCHIP CORPORATION
- Anand Pandurangan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS
- Publication number 20130159820
- Publication date Jun 20, 2013
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING