Shakti KAPOOR

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performance and reliability of processor store operation data trans...
- Patent number 12,141,071
- Issue date Nov 12, 2024
- International Business Machnes Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 12,130,749
- Issue date Oct 29, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence validation using delayed fulfillment of L2 requests
- Patent number 12,118,355
- Issue date Oct 15, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 11,620,235
- Issue date Apr 4, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-silicon chip model of extracted workload inner loop instruction...
- Patent number 11,501,046
- Issue date Nov 15, 2022
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor performance monitor that logs reasons for reservation loss
- Patent number 11,347,505
- Issue date May 31, 2022
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for reducing processor latency
- Patent number 11,163,704
- Issue date Nov 2, 2021
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Uncore input/output latency analysis
- Patent number 11,151,011
- Issue date Oct 19, 2021
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 11,094,391
- Issue date Aug 17, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 11,061,821
- Issue date Jul 13, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory performance and footprint
- Patent number 10,983,798
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory performance and footprint
- Patent number 10,977,043
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling segment layout in a stress test for a processor memory...
- Patent number 10,877,864
- Issue date Dec 29, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing processor errors
- Patent number 10,748,637
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently generating effective address translations for memory ma...
- Patent number 10,713,179
- Issue date Jul 14, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor performance monitor that logs reasons for reservation loss
- Patent number 10,579,376
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress testing a processor memory with a link stack
- Patent number 10,540,249
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded page size hint for page fault resolution
- Patent number 10,528,476
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 10,521,355
- Issue date Dec 31, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,489,261
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replicating test case data into a cache with non-naturally aligned...
- Patent number 10,489,259
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for reducing processor latency
- Patent number 10,482,040
- Issue date Nov 19, 2019
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,481,991
- Issue date Nov 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 10,438,682
- Issue date Oct 8, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Transactional memory operation success rate
- Patent number 10,417,131
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory operation success rate
- Patent number 10,417,129
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently generating effective address translations for memory ma...
- Patent number 10,346,314
- Issue date Jul 9, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of correctness of interrupt triggers and delivery
- Patent number 10,318,456
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress testing a processor memory with a link stack
- Patent number 10,261,878
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying stale entries in address translation cache
- Patent number 10,261,917
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...
- Publication number 20240028518
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR
- Publication number 20230195981
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230195649
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS
- Publication number 20230122466
- Publication date Apr 20, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230105945
- Publication date Apr 6, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-SILICON CHIP MODEL OF EXTRACTED WORKLOAD INNER LOOP INSTRUCTION...
- Publication number 20210303766
- Publication date Sep 30, 2021
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNCORE INPUT/OUTPUT LATENCY ANALYSIS
- Publication number 20210099373
- Publication date Apr 1, 2021
- International Business Machines Corporation
- Shakti Kapoor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONTROLLING SEGMENT LAYOUT IN A STRESS TEST FOR A PROCESSOR MEMORY...
- Publication number 20200201728
- Publication date Jun 25, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR PERFORMANCE MONITOR THAT LOGS REASONS FOR RESERVATION LOSS
- Publication number 20200150961
- Publication date May 14, 2020
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20200089621
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR REDUCING PROCESSOR LATENCY
- Publication number 20200042467
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Testing Processor Errors
- Publication number 20200035319
- Publication date Jan 30, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190287639
- Publication date Sep 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...
- Publication number 20190227945
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190198132
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR REDUCING PROCESSOR LATENCY
- Publication number 20190196986
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20190188146
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF CORRECTNESS OF INTERRUPT TRIGGERS AND DELIVERY
- Publication number 20190138472
- Publication date May 9, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL MEMORY PERFORMANCE AND FOOTPRINT
- Publication number 20190079773
- Publication date Mar 14, 2019
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL MEMORY PERFORMANCE AND FOOTPRINT
- Publication number 20190079774
- Publication date Mar 14, 2019
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050314
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050315
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL MEMORY OPERATION SUCCESS RATE
- Publication number 20180322059
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL MEMORY OPERATION SUCCESS RATE
- Publication number 20180322060
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Shakti KAPOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK
- Publication number 20180267875
- Publication date Sep 20, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK
- Publication number 20180267876
- Publication date Sep 20, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...
- Publication number 20180157567
- Publication date Jun 7, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SPECULATIVE INSTRUCTION EXECUTION WITH TEST CASES PLACED IN...
- Publication number 20180129577
- Publication date May 10, 2018
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRIVING PERVASIVE COMMANDS USING BREAKPOINTS IN A HARDWARE-ACCELERA...
- Publication number 20180120379
- Publication date May 3, 2018
- International Business Machines Corporation
- Debapriya Chatterjee
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFYING STALE ENTRIES IN ADDRESS TRANSLATION CACHE
- Publication number 20180121365
- Publication date May 3, 2018
- International Business Machines Corporation
- Vinod Bussa
- G06 - COMPUTING CALCULATING COUNTING

Shakti KAPOOR

Person

Patents Grantslast 30 patents

Performance and reliability of processor store operation data trans...

Validation of store coherence relative to page translation invalida...

Cache coherence validation using delayed fulfillment of L2 requests

Validation of store coherence relative to page translation invalida...

Pre-silicon chip model of extracted workload inner loop instruction...

Processor performance monitor that logs reasons for reservation loss

Method, system, and apparatus for reducing processor latency

Uncore input/output latency analysis

List insertion in test segments with non-naturally aligned data bou...

Method, system, and apparatus for stress testing memory translation...

Transactional memory performance and footprint

Transactional memory performance and footprint

Controlling segment layout in a stress test for a processor memory...

System and method for testing processor errors

Efficiently generating effective address translations for memory ma...

Processor performance monitor that logs reasons for reservation loss

Stress testing a processor memory with a link stack

Embedded page size hint for page fault resolution

Method, system, and apparatus for stress testing memory translation...

Efficient testing of direct memory address translation

Replicating test case data into a cache with non-naturally aligned...

Method, system, and apparatus for reducing processor latency

Efficient testing of direct memory address translation

List insertion in test segments with non-naturally aligned data bou...

Transactional memory operation success rate

Transactional memory operation success rate

Efficiently generating effective address translations for memory ma...

Validation of correctness of interrupt triggers and delivery

Stress testing a processor memory with a link stack

Identifying stale entries in address translation cache

Patents Applicationslast 30 patents

PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...

HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

PRE-SILICON CHIP MODEL OF EXTRACTED WORKLOAD INNER LOOP INSTRUCTION...

UNCORE INPUT/OUTPUT LATENCY ANALYSIS

CONTROLLING SEGMENT LAYOUT IN A STRESS TEST FOR A PROCESSOR MEMORY...

PROCESSOR PERFORMANCE MONITOR THAT LOGS REASONS FOR RESERVATION LOSS

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

METHOD, SYSTEM, AND APPARATUS FOR REDUCING PROCESSOR LATENCY

System and Method for Testing Processor Errors

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

EFFICIENTLY GENERATING EFFECTIVE ADDRESS TRANSLATIONS FOR MEMORY MA...

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

METHOD, SYSTEM, AND APPARATUS FOR REDUCING PROCESSOR LATENCY

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

VALIDATION OF CORRECTNESS OF INTERRUPT TRIGGERS AND DELIVERY

TRANSACTIONAL MEMORY PERFORMANCE AND FOOTPRINT

TRANSACTIONAL MEMORY PERFORMANCE AND FOOTPRINT

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION

TRANSACTIONAL MEMORY OPERATION SUCCESS RATE

TRANSACTIONAL MEMORY OPERATION SUCCESS RATE

STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK

STRESS TESTING A PROCESSOR MEMORY WITH A LINK STACK

REPLICATING TEST CASE DATA INTO A CACHE WITH NON-NATURALLY ALIGNED...

TESTING SPECULATIVE INSTRUCTION EXECUTION WITH TEST CASES PLACED IN...

DRIVING PERVASIVE COMMANDS USING BREAKPOINTS IN A HARDWARE-ACCELERA...

IDENTIFYING STALE ENTRIES IN ADDRESS TRANSLATION CACHE