Shanggar Periaman

Person

Penang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked package assembly with voltage reference plane
- Patent number 10,403,604
- Issue date Sep 3, 2019
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible packaging architecture
- Patent number 10,396,038
- Issue date Aug 27, 2019
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die semiconductor structure with intermediate vertical side c...
- Patent number 9,812,425
- Issue date Nov 7, 2017
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible system-in-package solutions for wearable devices
- Patent number 9,778,688
- Issue date Oct 3, 2017
- Intel Corporation
- Jiamiao Tang
- A43 - FOOTWEAR
Information Patent Grant
High density second level interconnection for bumpless build up lay...
- Patent number 9,721,878
- Issue date Aug 1, 2017
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging techniques and configurations for smal...
- Patent number 9,646,953
- Issue date May 9, 2017
- Intel Corporation
- Jackson Chung Peng Kong
- B43 - WRITING OR DRAWING IMPLEMENTS BUREAU ACCESSORIES
Information Patent Grant
Multi-die semiconductor structure with intermediate vertical side c...
- Patent number 9,478,524
- Issue date Oct 25, 2016
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to enable controlled side chip interconnection for 3D integr...
- Patent number 9,136,251
- Issue date Sep 15, 2015
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-density inter-package connections for ultra-thin package-on-pa...
- Patent number 8,987,896
- Issue date Mar 24, 2015
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die package
- Patent number 8,697,495
- Issue date Apr 15, 2014
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Firmware verification using system memory error check logic
- Patent number 8,281,229
- Issue date Oct 2, 2012
- Intel Corporation
- Yen Hsiang Chew
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Die backside wire bond technology for single or stacked die package
- Patent number 8,198,716
- Issue date Jun 12, 2012
- Intel Corporation
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die backside metallization and surface activated bonding for stacke...
- Patent number 8,110,930
- Issue date Feb 7, 2012
- Intel Corporation
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked die package
- Patent number 8,044,497
- Issue date Oct 25, 2011
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bandwidth allocation for network packet traffic
- Patent number 7,773,504
- Issue date Aug 10, 2010
- Intel Corporation
- Yen Hsiang Chew
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Quality of service (QoS) processing of data packets
- Patent number 7,743,181
- Issue date Jun 22, 2010
- Intel Corporation
- Yen Hsiang Chew
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Stacked-die packages with silicon vias and surface activated bonding
- Patent number 7,692,278
- Issue date Apr 6, 2010
- Intel Corporation
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package on package design to improve functionality and efficiency
- Patent number 7,400,033
- Issue date Jul 15, 2008
- Intel Corporation
- Bok Eng Cheah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked die semiconductor package
- Patent number 7,279,795
- Issue date Oct 9, 2007
- Intel Corporation
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE
- Publication number 20180294252
- Publication date Oct 11, 2018
- Intel Corporation
- Bok Eng CHEAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAY...
- Publication number 20180145014
- Publication date May 24, 2018
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLEXIBLE PACKAGING ARCHITECTURE
- Publication number 20170345763
- Publication date Nov 30, 2017
- Intel Corporation
- Bok Eng CHEAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE C...
- Publication number 20170018530
- Publication date Jan 19, 2017
- Bok Eng CHEAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGING TECHNIQUES AND CONFIGURATIONS FOR SMAL...
- Publication number 20160343686
- Publication date Nov 24, 2016
- Intel Corporation
- Jackson Chung Peng Kong
- B43 - WRITING OR DRAWING IMPLEMENTS BUREAU ACCESSORIES
Information Patent Application
FLEXIBLE SYSTEM-IN-PACKAGE SOLUTIONS FOR WEARABLE DEVICES
- Publication number 20160327977
- Publication date Nov 10, 2016
- Intel Corporation
- Jiamiao Tang
- A41 - WEARING APPAREL
Information Patent Application
MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE C...
- Publication number 20160005718
- Publication date Jan 7, 2016
- Bok Eng CHEAH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PA...
- Publication number 20150201497
- Publication date Jul 16, 2015
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DIE PACKAGE
- Publication number 20140175670
- Publication date Jun 26, 2014
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAY...
- Publication number 20140091442
- Publication date Apr 3, 2014
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD TO ENABLE CONTROLLED SIDE CHIP INTERCONNECTION FOR 3D INTEGR...
- Publication number 20130341803
- Publication date Dec 26, 2013
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CO...
- Publication number 20120319293
- Publication date Dec 20, 2012
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DIE PACKAGE
- Publication number 20120003792
- Publication date Jan 5, 2012
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PA...
- Publication number 20110140268
- Publication date Jun 16, 2011
- Bok Eng Cheah
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
FIRMWARE VERIFICATION USING SYSTEM MEMORY ERROR CHECK LOGIC
- Publication number 20100169750
- Publication date Jul 1, 2010
- Yen Hsiang Chew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bandwidth allocation for network packet traffic
- Publication number 20090122702
- Publication date May 14, 2009
- Yen Hsiang Chew
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
STACKED DIE PACKAGE
- Publication number 20090065951
- Publication date Mar 12, 2009
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Quality of Service (QoS) Processing of Data Packets
- Publication number 20090019196
- Publication date Jan 15, 2009
- Intel Corporation
- Yen Hsiang Chew
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE
- Publication number 20080315388
- Publication date Dec 25, 2008
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Die backside metallization and surface activated bonding for stacke...
- Publication number 20080315421
- Publication date Dec 25, 2008
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Die backside wire bond technology for single or stacked die package
- Publication number 20080237310
- Publication date Oct 2, 2008
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ON PACKAGE DESIGN TO IMPROVE FUNCTIONALITY AND EFFICIENCY
- Publication number 20080157350
- Publication date Jul 3, 2008
- Bok Eng Cheah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked die semiconductor package
- Publication number 20070152313
- Publication date Jul 5, 2007
- Shanggar Periaman
- H01 - BASIC ELECTRIC ELEMENTS

Shanggar Periaman

Person

Patents Grantslast 30 patents

Stacked package assembly with voltage reference plane

Flexible packaging architecture

Multi-die semiconductor structure with intermediate vertical side c...

Flexible system-in-package solutions for wearable devices

High density second level interconnection for bumpless build up lay...

Integrated circuit packaging techniques and configurations for smal...

Multi-die semiconductor structure with intermediate vertical side c...

Method to enable controlled side chip interconnection for 3D integr...

High-density inter-package connections for ultra-thin package-on-pa...

Stacked die package

Firmware verification using system memory error check logic

Die backside wire bond technology for single or stacked die package

Die backside metallization and surface activated bonding for stacke...

Stacked die package

Bandwidth allocation for network packet traffic

Quality of service (QoS) processing of data packets

Stacked-die packages with silicon vias and surface activated bonding

Package on package design to improve functionality and efficiency

Stacked die semiconductor package

Patents Applicationslast 30 patents

STACKED PACKAGE ASSEMBLY WITH VOLTAGE REFERENCE PLANE

HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAY...

FLEXIBLE PACKAGING ARCHITECTURE

MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE C...

INTEGRATED CIRCUIT PACKAGING TECHNIQUES AND CONFIGURATIONS FOR SMAL...

FLEXIBLE SYSTEM-IN-PACKAGE SOLUTIONS FOR WEARABLE DEVICES

MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE C...

HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PA...

STACKED DIE PACKAGE

HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAY...

METHOD TO ENABLE CONTROLLED SIDE CHIP INTERCONNECTION FOR 3D INTEGR...

MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CO...

STACKED DIE PACKAGE

HIGH-DENSITY INTER-PACKAGE CONNECTIONS FOR ULTRA-THIN PACKAGE-ON-PA...

FIRMWARE VERIFICATION USING SYSTEM MEMORY ERROR CHECK LOGIC

Bandwidth allocation for network packet traffic

STACKED DIE PACKAGE

Quality of Service (QoS) Processing of Data Packets

VERTICAL CONTROLLED SIDE CHIP CONNECTION FOR 3D PROCESSOR PACKAGE

Die backside metallization and surface activated bonding for stacke...

Die backside wire bond technology for single or stacked die package

PACKAGE ON PACKAGE DESIGN TO IMPROVE FUNCTIONALITY AND EFFICIENCY

Stacked die semiconductor package