Shangzhi Sun

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Local retiming optimization for circuit designs
- Patent number 10,678,983
- Issue date Jun 9, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic pipelining of memory circuits
- Patent number 10,664,561
- Issue date May 26, 2020
- Xilinx, Inc.
- Pradip K. Kar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying equivalence of design latency
- Patent number 10,606,979
- Issue date Mar 31, 2020
- Xilinx, Inc.
- Shangzhi Sun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelizing timing-based operations for circuit designs
- Patent number 10,303,833
- Issue date May 28, 2019
- Xilinx, Inc.
- Aman Gayasen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design transformation for automatic latency reduction
- Patent number 10,289,786
- Issue date May 14, 2019
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescaling
- Patent number 9,257,986
- Issue date Feb 9, 2016
- Altera Corporation
- Scott J. Weber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Rescaling
- Patent number 8,788,987
- Issue date Jul 22, 2014
- Tabula, Inc.
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescaling
- Patent number 8,650,514
- Issue date Feb 11, 2014
- Tabula, Inc.
- Scott J. Weber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Detection of timing errors in programmable logic devices
- Patent number 7,831,856
- Issue date Nov 9, 2010
- Lattice Semiconductor Corporation
- Liren Liu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES
- Publication number 20240256749
- Publication date Aug 1, 2024
- Xilinx, Inc.
- Chaithanya Dudha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rescaling
- Publication number 20140210512
- Publication date Jul 31, 2014
- Tabula, Inc.
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rescaling
- Publication number 20130097575
- Publication date Apr 18, 2013
- Tabula, Inc.
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESCALING
- Publication number 20120176155
- Publication date Jul 12, 2012
- Tabula, Inc.
- Scott J. Weber
- G06 - COMPUTING CALCULATING COUNTING

Shangzhi Sun

Person

Patents Grantslast 30 patents

Local retiming optimization for circuit designs

Automatic pipelining of memory circuits

Verifying equivalence of design latency

Parallelizing timing-based operations for circuit designs

Circuit design transformation for automatic latency reduction

Rescaling

Rescaling

Rescaling

Detection of timing errors in programmable logic devices

Patents Applicationslast 30 patents

RETIMING SEQUENTIAL ELEMENTS HAVING INITITAL STATES

Rescaling

Rescaling

RESCALING