Shankar P. Sinha

Person

Redwood City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,984,734
- Issue date May 29, 2018
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,607,671
- Issue date Mar 28, 2017
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiport memory element circuitry
- Patent number 9,576,617
- Issue date Feb 21, 2017
- Altera Corporation
- Shih-Lin S. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 9,496,268
- Issue date Nov 15, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with p-type diffusion read-only port
- Patent number 9,401,200
- Issue date Jul 26, 2016
- Altera Corporation
- Mark T. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,299,396
- Issue date Mar 29, 2016
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory elements with stacked pull-up devices
- Patent number 9,276,083
- Issue date Mar 1, 2016
- Altera Corporation
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit including memory devices, a freeze circuit and a tes...
- Patent number 9,111,641
- Issue date Aug 18, 2015
- Altera Corporation
- Rakesh H. Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-voltage programmable electrical fuses
- Patent number 9,006,794
- Issue date Apr 14, 2015
- Altera Corporation
- Shuang Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with asymmetric transistors
- Patent number 8,995,177
- Issue date Mar 31, 2015
- Altera Corporation
- Shankar Sinha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for reducing leakage current in memory arrays
- Patent number 8,861,283
- Issue date Oct 14, 2014
- Altera Corporation
- Brian Yung Fun Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiport memory element circuitry
- Patent number 8,755,218
- Issue date Jun 17, 2014
- Altera Corporation
- Shih-Lin S. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,750,026
- Issue date Jun 10, 2014
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric transistors
- Patent number 8,638,594
- Issue date Jan 28, 2014
- Altera Corporation
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random-access memory having read circuitry with capacitive s...
- Patent number 8,619,464
- Issue date Dec 31, 2013
- Altera Corporation
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Grant
3T device based memory circuits and arrays
- Patent number 8,599,598
- Issue date Dec 3, 2013
- Altera Corporation
- Rakesh H. Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,482,963
- Issue date Jul 9, 2013
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory element circuitry with stressed transistors
- Patent number 8,218,353
- Issue date Jul 10, 2012
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
MEMS switching device and conductive bridge device based circuits
- Patent number 8,130,559
- Issue date Mar 6, 2012
- Altera Corporation
- Rakesh H. Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
SEU resistant SRAM using feedback MOSFET
- Patent number 6,775,178
- Issue date Aug 10, 2004
- Honeywell International Inc.
- Michael S. Liu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Asymmetrical Memory Circuits And Methods
- Publication number 20230410897
- Publication date Dec 21, 2023
- Intel Corporation
- David Parkhouse
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20170200484
- Publication date Jul 13, 2017
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20160232952
- Publication date Aug 11, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20150318029
- Publication date Nov 5, 2015
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES
- Publication number 20140169074
- Publication date Jun 19, 2014
- Altera Corporation
- Shankar Sinha
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPORT MEMORY ELEMENT CIRCUITRY
- Publication number 20120311401
- Publication date Dec 6, 2012
- Shih-Lin S. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
High speed SOI transistors
- Publication number 20030189227
- Publication date Oct 9, 2003
- Honeywell International Inc.
- Michael S. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEU resistant SRAM using feedback MOSFET
- Publication number 20030189847
- Publication date Oct 9, 2003
- Honeywell International Inc.
- Michael S. Liu
- G11 - INFORMATION STORAGE

Shankar P. Sinha

Person

Patents Grantslast 30 patents

Programmable integrated circuits with in-operation reconfiguration...

Programmable integrated circuits with in-operation reconfiguration...

Multiport memory element circuitry

Integrated circuits with asymmetric and stacked transistors

Memory cells with p-type diffusion read-only port

Programmable integrated circuits with in-operation reconfiguration...

Memory elements with stacked pull-up devices

Memory circuit including memory devices, a freeze circuit and a tes...

Low-voltage programmable electrical fuses

Integrated circuits with asymmetric transistors

Systems and methods for reducing leakage current in memory arrays

Multiport memory element circuitry

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with asymmetric transistors

Static random-access memory having read circuitry with capacitive s...

3T device based memory circuits and arrays

Integrated circuits with asymmetric and stacked transistors

Memory element circuitry with stressed transistors

MEMS switching device and conductive bridge device based circuits

SEU resistant SRAM using feedback MOSFET

Patents Applicationslast 30 patents

Asymmetrical Memory Circuits And Methods

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

Integrated Circuits with Asymmetric and Stacked Transistors

Integrated Circuits with Asymmetric and Stacked Transistors

MEMORY ELEMENTS WITH STACKED PULL-UP DEVICES

MULTIPORT MEMORY ELEMENT CIRCUITRY

High speed SOI transistors

SEU resistant SRAM using feedback MOSFET