Shanker Singh

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for memory with embedded processor
- Patent number 6,877,046
- Issue date Apr 5, 2005
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for detecting a hard failure in a memory array
- Patent number 6,799,291
- Issue date Sep 28, 2004
- International Business Machines Corporation
- Charles Arthur Kilmer
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault tolerant memory system utilizing memory arrays with hard erro...
- Patent number 6,785,837
- Issue date Aug 31, 2004
- International Business Machines Corporation
- Charles Arthur Kilmer
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance fault tolerant memory system utilizing greater tha...
- Patent number 6,732,291
- Issue date May 4, 2004
- International Business Machines Corporation
- Charles Arthur Kilmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array system
- Patent number 6,728,156
- Issue date Apr 27, 2004
- International Business Machines Corporation
- Charles A. Kilmer
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed radix 100 parallel adder
- Patent number 6,546,411
- Issue date Apr 8, 2003
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for efficiently storing compressed data on a hard...
- Patent number 6,449,689
- Issue date Sep 10, 2002
- International Business Machines Corporation
- Brian Jeffrey Corcoran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for storing compressed and uncompressed data on a...
- Patent number 6,360,300
- Issue date Mar 19, 2002
- International Business Machines Corporation
- Brian Jeffrey Corcoran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data caching with a partially compressed cache
- Patent number 6,324,621
- Issue date Nov 27, 2001
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing linear address mapped storage und...
- Patent number 6,178,489
- Issue date Jan 23, 2001
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing on-chip function checks and loc...
- Patent number 6,105,155
- Issue date Aug 15, 2000
- International Business Machines Corporation
- Joe-Ming Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting and correcting anomalies in fiel...
- Patent number 6,101,624
- Issue date Aug 8, 2000
- International Business Machines Corporation
- Joe-Ming Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array based data reorganizer
- Patent number 5,873,126
- Issue date Feb 16, 1999
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-tolerant method and means for managing access to an initial p...
- Patent number 5,832,005
- Issue date Nov 3, 1998
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array based data reorganizer
- Patent number 5,485,588
- Issue date Jan 16, 1996
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault mapping apparatus for memory
- Patent number 5,233,614
- Issue date Aug 3, 1993
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory correction scheme using spare arrays
- Patent number 4,584,681
- Issue date Apr 22, 1986
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable memory using both address permutation and spare memo...
- Patent number 4,584,682
- Issue date Apr 22, 1986
- International Business Machines Corporation
- Siddharth R. Shah
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault alignment control system and circuits
- Patent number 4,534,029
- Issue date Aug 6, 1985
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of memory reconfiguration for fault tolerant memory
- Patent number 4,485,471
- Issue date Nov 27, 1984
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated binary-BCD look-ahead adder
- Patent number 4,118,786
- Issue date Oct 3, 1978
- International Business Machines Corporation
- Samuel R. Levine
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for memory with embedded processor
- Publication number 20030188086
- Publication date Oct 2, 2003
- International Business Machines Corporation
- Shanker Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory array system
- Publication number 20030169634
- Publication date Sep 11, 2003
- International Business Machines Corporation
- Charles A. Kilmer
- G11 - INFORMATION STORAGE
Information Patent Application
DATA CACHING WITH A PARTIALLY COMPRESSED CACHE
- Publication number 20010001872
- Publication date May 24, 2001
- INTERNATIONAL BUSINESS MACHINES CORP.
- SHANKER SINGH
- G06 - COMPUTING CALCULATING COUNTING

Shanker Singh

Person

Patents Grantslast 30 patents

Method and apparatus for memory with embedded processor

Method and system for detecting a hard failure in a memory array

Fault tolerant memory system utilizing memory arrays with hard erro...

High performance fault tolerant memory system utilizing greater tha...

Memory array system

High-speed radix 100 parallel adder

System and method for efficiently storing compressed data on a hard...

System and method for storing compressed and uncompressed data on a...

Data caching with a partially compressed cache

Method and apparatus for managing linear address mapped storage und...

Method and apparatus for performing on-chip function checks and loc...

Method and apparatus for detecting and correcting anomalies in fiel...

Memory array based data reorganizer

Fault-tolerant method and means for managing access to an initial p...

Memory array based data reorganizer

Fault mapping apparatus for memory

Memory correction scheme using spare arrays

Reconfigurable memory using both address permutation and spare memo...

Fault alignment control system and circuits

Method of memory reconfiguration for fault tolerant memory

Integrated binary-BCD look-ahead adder

Patents Applicationslast 30 patents

Method and apparatus for memory with embedded processor

Memory array system

DATA CACHING WITH A PARTIALLY COMPRESSED CACHE