Shantanu Gupta

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction and logic for a binary translation mechanism for contro...
- Patent number 10,048,965
- Issue date Aug 14, 2018
- Intel Corporation
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for a binary translation mechanism for contro...
- Patent number 9,606,941
- Issue date Mar 28, 2017
- Intel Corporation
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System of improved loop detection and execution
- Patent number 9,459,871
- Issue date Oct 4, 2016
- Intel Corporation
- Masha Lipshits
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for a binary translation mechanism for contro...
- Patent number 9,330,028
- Issue date May 3, 2016
- Intel Corporation
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing local power gating in a processor
- Patent number 9,229,524
- Issue date Jan 5, 2016
- Intel Corporation
- Nadav Bonen
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for dynamic allocation of multiple buffers in...
- Patent number 5,778,245
- Issue date Jul 7, 1998
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for binding instructions to dispatch ports of...
- Patent number 5,689,674
- Issue date Nov 18, 1997
- Intel Corporation
- James S. Griffith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for entry allocation for a buffer resource uti...
- Patent number 5,627,984
- Issue date May 6, 1997
- Intel Corporation
- Shantanu R. Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entry allocation in a circular buffer
- Patent number 5,584,037
- Issue date Dec 10, 1996
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entry allocation in a circular buffer using wrap bits indicating wh...
- Patent number 5,584,038
- Issue date Dec 10, 1996
- Intel Corporation
- David B. Papworth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entry allocation apparatus and method of same
- Patent number 5,560,025
- Issue date Sep 24, 1996
- Intel Corporation
- Shantanu R. Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partial and full stall handling in allocation
- Patent number 5,524,263
- Issue date Jun 4, 1996
- Intel Corporation
- James S. Griffth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for entry allocation for a resource buffer
- Patent number 5,490,280
- Issue date Feb 6, 1996
- Intel Corporation
- Shantanu R. Gupta
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Instruction and Logic for a Binary Translation Mechanism for Contro...
- Publication number 20170242702
- Publication date Aug 24, 2017
- Intel Corporation
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for a Binary Translation Mechanism for Contro...
- Publication number 20160239438
- Publication date Aug 18, 2016
- Intel Corporation
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20160085287
- Publication date Mar 24, 2016
- Intel Corporation
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for a Binary Translation Mechanism for Contro...
- Publication number 20150278126
- Publication date Oct 1, 2015
- Petros Maniatis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM OF IMPROVED LOOP DETECTION AND EXECUTION
- Publication number 20140189331
- Publication date Jul 3, 2014
- Maria Lipshits
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Performing Local Power Gating In A Processor
- Publication number 20140006817
- Publication date Jan 2, 2014
- Nadav Bonen
- G06 - COMPUTING CALCULATING COUNTING

Shantanu Gupta

Person

Patents Grantslast 30 patents

Instruction and logic for a binary translation mechanism for contro...

Instruction and logic for a binary translation mechanism for contro...

System of improved loop detection and execution

Instruction and logic for a binary translation mechanism for contro...

Performing local power gating in a processor

Method and apparatus for dynamic allocation of multiple buffers in...

Method and apparatus for binding instructions to dispatch ports of...

Apparatus and method for entry allocation for a buffer resource uti...

Entry allocation in a circular buffer

Entry allocation in a circular buffer using wrap bits indicating wh...

Entry allocation apparatus and method of same

Method and apparatus for partial and full stall handling in allocation

Apparatus and method for entry allocation for a resource buffer

Patents Applicationslast 30 patents

Instruction and Logic for a Binary Translation Mechanism for Contro...

Instruction and Logic for a Binary Translation Mechanism for Contro...

Performing Local Power Gating In A Processor

Instruction and Logic for a Binary Translation Mechanism for Contro...

SYSTEM OF IMPROVED LOOP DETECTION AND EXECUTION

Performing Local Power Gating In A Processor