SHANTANU R. RAJWADE

Person

SANTA CLARA, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configuration of a memory device for programming memory cells
- Patent number 11,721,396
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 11,698,725
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 11,182,074
- Issue date Nov 23, 2021
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using variable voltages to discharge electrons from a memory array...
- Patent number 11,139,036
- Issue date Oct 5, 2021
- Intel Corporation
- Tarek Ahmed Ameen Beshari
- G11 - INFORMATION STORAGE
Information Patent Grant
Device, system, and method to verify data programming of a multi-le...
- Patent number 11,094,386
- Issue date Aug 17, 2021
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Boosted bitlines for storage cell programmed state verification in...
- Patent number 11,056,203
- Issue date Jul 6, 2021
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
SSD having a parallelized, multi-level program voltage verification
- Patent number 11,004,524
- Issue date May 11, 2021
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration of a memory device for programming memory cells
- Patent number 10,777,277
- Issue date Sep 15, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for dynamically determining start program volt...
- Patent number 10,714,186
- Issue date Jul 14, 2020
- Intel Corporation
- Purval Shyam Sule
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 10,658,053
- Issue date May 19, 2020
- Intel Corporation
- Shantanu R Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Operation of a memory device during programming
- Patent number 10,482,974
- Issue date Nov 19, 2019
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Segmented erase in memory
- Patent number 10,453,535
- Issue date Oct 22, 2019
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer operations in memory
- Patent number 10,430,114
- Issue date Oct 1, 2019
- Micron Technology, Inc.
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 10,379,738
- Issue date Aug 13, 2019
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improving sequential reading in NAND flash
- Patent number 10,289,313
- Issue date May 14, 2019
- Intel Corporation
- Han Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically determining start program volt...
- Patent number 10,224,107
- Issue date Mar 5, 2019
- Intel Corporation
- Purval Shyam Sule
- G11 - INFORMATION STORAGE
Information Patent Grant
Predictive count fail byte (CFBYTE) for non-volatile memory
- Patent number 10,141,071
- Issue date Nov 27, 2018
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer operations in memory
- Patent number 9,977,622
- Issue date May 22, 2018
- Micron Technology, Inc.
- Pranav Kalavade
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple memory...
- Patent number 9,910,594
- Issue date Mar 6, 2018
- Micron Technology, Inc.
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing read operations on a memory device
- Patent number 9,865,357
- Issue date Jan 9, 2018
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing data program completion overhead...
- Patent number 9,852,065
- Issue date Dec 26, 2017
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 9,792,997
- Issue date Oct 17, 2017
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for protecting lower page data during programm...
- Patent number 9,703,494
- Issue date Jul 11, 2017
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 9,418,752
- Issue date Aug 16, 2016
- Intel Corporation
- Shantanu R Rajwade
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SIMULTANEOUS STATISTICAL MULTI-SUBBLOCK VERIFY FOR NAND MEMORIES
- Publication number 20240136002
- Publication date Apr 25, 2024
- Intel NDTM US LLC
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT BITLINE STABILIZATION FOR PROGRAM INHIBIT IN NAND ARRAYS
- Publication number 20240136003
- Publication date Apr 25, 2024
- Intel NDTM US LLC
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
FAST AND EFFICIENT VERIFY RECOVERY AND ARRAY DISCHARGE FOR 3D NAND...
- Publication number 20240071532
- Publication date Feb 29, 2024
- Intel NDTM US LLC
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20240013840
- Publication date Jan 11, 2024
- Lodestar Licensing Group, LLC
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
POWER EFFICIENT ARRAY DISCHARGE FOR PROGRAM BOOSTING
- Publication number 20230352092
- Publication date Nov 2, 2023
- Intel NDTM US LLC
- Tarek Ameen
- G11 - INFORMATION STORAGE
Information Patent Application
SYNCHRONOUS INDEPENDENT PLANE READ OPERATION
- Publication number 20230317144
- Publication date Oct 5, 2023
- Intel NDTM US LLC
- Chang Wan Ha
- G11 - INFORMATION STORAGE
Information Patent Application
SKIP PROGRAM VERIFY FOR DYNAMIC START VOLTAGE SAMPLING
- Publication number 20230161478
- Publication date May 25, 2023
- Intel NDTM US LLC
- Archana TANKASALA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPROVING WRITE UNIFORMITY IN A MEMORY DEVICE
- Publication number 20230154539
- Publication date May 18, 2023
- Intel Corporation
- Shantanu R. Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC GATE STEPS FOR LAST-LEVEL PROGRAMMING TO IMPROVE WRITE PERF...
- Publication number 20230061293
- Publication date Mar 2, 2023
- Intel Corporation
- Sagar Upadhyay
- G11 - INFORMATION STORAGE
Information Patent Application
PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROV...
- Publication number 20230044991
- Publication date Feb 9, 2023
- Intel Corporation
- Shantanu Rajwade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM VERIFY PROCESS HAVING PLACEMENT AWARE PRE-PROGRAM VERIFY (P...
- Publication number 20220366991
- Publication date Nov 17, 2022
- Intel Corporation
- Shantanu R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR...
- Publication number 20220310178
- Publication date Sep 29, 2022
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SIMULTANEOUS PROGRAMMING OF MULTIPLE SUB-BLOCKS IN NAND MEMORY STRU...
- Publication number 20220310160
- Publication date Sep 29, 2022
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC DETECTION AND DYNAMIC ADJUSTMENT OF SUB-THRESHOLD SWING IN...
- Publication number 20220208286
- Publication date Jun 30, 2022
- Intel Corporation
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERA...
- Publication number 20220172784
- Publication date Jun 2, 2022
- Intel Corporation
- Shantanu R. RAJWADE
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...
- Publication number 20220155958
- Publication date May 19, 2022
- Micron Technology, Inc.
- SHANTANU R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, SYSTEM, AND METHOD TO VERIFY DATA PROGRAMMING OF A MULTI-LE...
- Publication number 20210257036
- Publication date Aug 19, 2021
- Intel Corporation
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Application
USING VARIABLE VOLTAGES TO DISCHARGE ELECTRONS FROM A MEMORY ARRAY...
- Publication number 20210249092
- Publication date Aug 12, 2021
- Intel Corporation
- Tarek Ahmed AMEEN BESHARI
- G11 - INFORMATION STORAGE
Information Patent Application
SSD HAVING A PARALLELIZED, MULTI-LEVEL PROGRAM VOLTAGE VERIFICATION
- Publication number 20210104285
- Publication date Apr 8, 2021
- Intel Corporation
- Xiang YANG
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20200402586
- Publication date Dec 24, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SOLID STATE DRIVE (SSD) WITH IN-FLIGHT ERASURE ITERATION SUSPENSION
- Publication number 20200135284
- Publication date Apr 30, 2020
- Intel Corporation
- Justin R. DAYACAP
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS
- Publication number 20200066350
- Publication date Feb 27, 2020
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING START PROGRAM VOLT...
- Publication number 20190304543
- Publication date Oct 3, 2019
- Intel Corporation
- Purval Shyam Sule
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...
- Publication number 20190258404
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- SHANTANU R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEMPERATURE-DEPENDENT READ OPERATION TIME ADJUSTMENT IN NON-VOLATIL...
- Publication number 20190043567
- Publication date Feb 7, 2019
- Intel Corporation
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR DETECTING FAILURE OF PROGRAMMING...
- Publication number 20190006016
- Publication date Jan 3, 2019
- Intel Corporation
- Ali KHAKIFIROOZ
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER OPERATIONS IN MEMORY
- Publication number 20180217782
- Publication date Aug 2, 2018
- Micron Technology, Inc.
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER OPERATIONS IN MEMORY
- Publication number 20180143784
- Publication date May 24, 2018
- Micron Technology, Inc.
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...
- Publication number 20180136845
- Publication date May 17, 2018
- Micron Technology, Inc.
- SHANTANU R. RAJWADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
- Publication number 20180122487
- Publication date May 3, 2018
- Intel Corporation
- Shantanu R. RAJWADE
- G11 - INFORMATION STORAGE

SHANTANU R. RAJWADE

Person

Patents Grantslast 30 patents

Configuration of a memory device for programming memory cells

Apparatuses and methods for concurrently accessing multiple memory...

Apparatuses and methods for concurrently accessing multiple memory...

Using variable voltages to discharge electrons from a memory array...

Device, system, and method to verify data programming of a multi-le...

Boosted bitlines for storage cell programmed state verification in...

SSD having a parallelized, multi-level program voltage verification

Configuration of a memory device for programming memory cells

Method and apparatus for dynamically determining start program volt...

Ramping inhibit voltage during memory programming

Operation of a memory device during programming

Segmented erase in memory

Buffer operations in memory

Apparatuses and methods for concurrently accessing multiple memory...

Method and apparatus for improving sequential reading in NAND flash

Method and apparatus for dynamically determining start program volt...

Predictive count fail byte (CFBYTE) for non-volatile memory

Buffer operations in memory

Apparatuses and methods for concurrently accessing multiple memory...

Performing read operations on a memory device

Method and apparatus for reducing data program completion overhead...

Ramping inhibit voltage during memory programming

Method and apparatus for protecting lower page data during programm...

Ramping inhibit voltage during memory programming

Patents Applicationslast 30 patents

SIMULTANEOUS STATISTICAL MULTI-SUBBLOCK VERIFY FOR NAND MEMORIES

EFFICIENT BITLINE STABILIZATION FOR PROGRAM INHIBIT IN NAND ARRAYS

FAST AND EFFICIENT VERIFY RECOVERY AND ARRAY DISCHARGE FOR 3D NAND...

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

POWER EFFICIENT ARRAY DISCHARGE FOR PROGRAM BOOSTING

SYNCHRONOUS INDEPENDENT PLANE READ OPERATION

SKIP PROGRAM VERIFY FOR DYNAMIC START VOLTAGE SAMPLING

METHOD AND APPARATUS FOR IMPROVING WRITE UNIFORMITY IN A MEMORY DEVICE

DYNAMIC GATE STEPS FOR LAST-LEVEL PROGRAMMING TO IMPROVE WRITE PERF...

PAGE MAP RENUMBERING TO REDUCE ERROR CORRECTION FAILURES AND IMPROV...

PROGRAM VERIFY PROCESS HAVING PLACEMENT AWARE PRE-PROGRAM VERIFY (P...

CACHE PROCESSES WITH ADAPTIVE DYNAMIC START VOLTAGE CALCULATION FOR...

SIMULTANEOUS PROGRAMMING OF MULTIPLE SUB-BLOCKS IN NAND MEMORY STRU...

DYNAMIC DETECTION AND DYNAMIC ADJUSTMENT OF SUB-THRESHOLD SWING IN...

MEMORY CELL SENSING CIRCUIT WITH ADJUSTED BIAS FROM PRE-BOOST OPERA...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...

DEVICE, SYSTEM, AND METHOD TO VERIFY DATA PROGRAMMING OF A MULTI-LE...

USING VARIABLE VOLTAGES TO DISCHARGE ELECTRONS FROM A MEMORY ARRAY...

SSD HAVING A PARALLELIZED, MULTI-LEVEL PROGRAM VOLTAGE VERIFICATION

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

SOLID STATE DRIVE (SSD) WITH IN-FLIGHT ERASURE ITERATION SUSPENSION

CONFIGURATION OF A MEMORY DEVICE FOR PROGRAMMING MEMORY CELLS

METHOD AND APPARATUS FOR DYNAMICALLY DETERMINING START PROGRAM VOLT...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...

TEMPERATURE-DEPENDENT READ OPERATION TIME ADJUSTMENT IN NON-VOLATIL...

METHOD, SYSTEM, AND APPARATUS FOR DETECTING FAILURE OF PROGRAMMING...

BUFFER OPERATIONS IN MEMORY

BUFFER OPERATIONS IN MEMORY

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE MEMORY...

RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING