Shantanu Sarangi

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Leveraging low power states for fault testing of processing cores a...
- Patent number 12,124,346
- Issue date Oct 22, 2024
- NVIDIA Corporation
- Jonah Alben
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for testing semiconductor devices
- Patent number 12,079,097
- Issue date Sep 3, 2024
- NVIDIA Corporation
- Animesh Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In system test of chips in functional systems
- Patent number 12,078,678
- Issue date Sep 3, 2024
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for isolating interfaces while testing semiconductor dev...
- Patent number 11,867,744
- Issue date Jan 9, 2024
- NVIDIA Corporation
- Animesh Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-system test of chips in functional systems
- Patent number 11,726,139
- Issue date Aug 15, 2023
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing testing utilizing staggered clocks
- Patent number 11,668,750
- Issue date Jun 6, 2023
- NVIDIA Corporation
- Sailendra Chadalavada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leveraging low power states for fault testing of processing cores a...
- Patent number 11,573,872
- Issue date Feb 7, 2023
- NVIDIA Corporation
- Jonah Alben
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling test networks of chips using integrated processors
- Patent number 11,526,644
- Issue date Dec 13, 2022
- NVIDIA Corporation
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware-controlled updating of a physical operating parameter for...
- Patent number 11,494,370
- Issue date Nov 8, 2022
- NVIDIA Corporation
- Sreedhar Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In system test of chips in functional systems
- Patent number 11,408,934
- Issue date Aug 9, 2022
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leveraging low power states for fault testing of processing cores a...
- Patent number 11,204,849
- Issue date Dec 21, 2021
- NVIDIA Corporation
- Jonah Alben
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip execution of in-system test utilizing a generalized test image
- Patent number 10,890,620
- Issue date Jan 12, 2021
- NVIDIA Corp.
- Milind Bhaiyyasaheb Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Field adaptable in-system test mechanisms
- Patent number 10,746,798
- Issue date Aug 18, 2020
- NVIDIA Corp.
- Sailendra Chadalavada
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus to access high volume test data over high spee...
- Patent number 10,663,515
- Issue date May 26, 2020
- NVIDIA Corp.
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Granular dynamic test systems and methods
- Patent number 10,545,189
- Issue date Jan 28, 2020
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Granular dynamic test systems and methods
- Patent number 10,481,203
- Issue date Nov 19, 2019
- NVIDIA Corporation
- Shantanu Sarangi
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic independent test partition clock
- Patent number 10,473,720
- Issue date Nov 12, 2019
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for dynamic standard test access (DSTA) for a log...
- Patent number 10,451,676
- Issue date Oct 22, 2019
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Grant
Independent test partition clock coordination across multiple test...
- Patent number 10,444,280
- Issue date Oct 15, 2019
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan system interface (SSI) module
- Patent number 10,317,463
- Issue date Jun 11, 2019
- NVIDIA Corporation
- Milind Sonawane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test partition external input/output interface control for test par...
- Patent number 10,281,524
- Issue date May 7, 2019
- NVIDIA Corporation
- Sailendra Chadalavda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
- Publication number 20250028620
- Publication date Jan 23, 2025
- NVIDIA Corporation
- Shantanu SARANGI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...
- Publication number 20240419568
- Publication date Dec 19, 2024
- NVIDIA Corporation
- Jonah ALBEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
- Publication number 20240227824
- Publication date Jul 11, 2024
- NVIDIA Corporation
- Anitha Kalva
- B60 - VEHICLES IN GENERAL
Information Patent Application
ASYNCHRONOUS IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS
- Publication number 20240132083
- Publication date Apr 25, 2024
- NVIDIA Corporation
- Anitha Kalva
- B60 - VEHICLES IN GENERAL
Information Patent Application
IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS
- Publication number 20230349970
- Publication date Nov 2, 2023
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR ENABLING ON-DIE NOISE MEASUREMENT DURING ATE TESTING...
- Publication number 20230146920
- Publication date May 11, 2023
- NVIDIA Corporation
- Bonita Bhaskaran
- G01 - MEASURING TESTING
Information Patent Application
LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...
- Publication number 20230123956
- Publication date Apr 20, 2023
- NVIDIA Corporation
- Jonah ALBEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING TESTING UTILIZING STAGGERED CLOCKS
- Publication number 20230089800
- Publication date Mar 23, 2023
- NVIDIA Corporation
- Sailendra Chadalavada
- G01 - MEASURING TESTING
Information Patent Application
IN-SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS
- Publication number 20220382659
- Publication date Dec 1, 2022
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RUNTIME IN-SYSTEM TESTING
- Publication number 20220365857
- Publication date Nov 17, 2022
- NVIDIA Corporation
- Sailendra Chadalavada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING TEST NETWORKS OF CHIPS USING INTEGRATED PROCESSORS
- Publication number 20220138387
- Publication date May 5, 2022
- NVIDIA Corporation
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ISOLATING INTERFACES WHILE TESTING SEMICONDUCTOR DEV...
- Publication number 20220120804
- Publication date Apr 21, 2022
- NVIDIA Corporation
- Animesh KHARE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR TESTING SEMICONDUCTOR DEVICES
- Publication number 20220121542
- Publication date Apr 21, 2022
- NVIDIA Corporation
- Animesh KHARE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...
- Publication number 20220114069
- Publication date Apr 14, 2022
- NVIDIA Corporation
- Jonah ALBEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE-CONTROLLED UPDATING OF A PHYSICAL OPERATING PARAMETER FOR...
- Publication number 20210294791
- Publication date Sep 23, 2021
- NVIDIA Corporation
- Sreedhar Narayanaswamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...
- Publication number 20210286693
- Publication date Sep 16, 2021
- Jonah ALBEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP EXECUTION OF IN-SYSTEM TEST UTILIZING A GENERALIZED TEST IMAGE
- Publication number 20200363470
- Publication date Nov 19, 2020
- NVIDIA Corp.
- Milind Bhaiyyasaheb Sonawane
- G01 - MEASURING TESTING
Information Patent Application
IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS
- Publication number 20190195947
- Publication date Jun 27, 2019
- NVIDIA Corporation
- Shantanu Sarangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO ACCESS HIGH VOLUME TEST DATA OVER HIGH SPEE...
- Publication number 20190128964
- Publication date May 2, 2019
- NVIDIA Corp.
- Kaushik Narayanun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170205465
- Publication date Jul 20, 2017
- NVIDIA Corporation
- Shantanu SARANGI
- G01 - MEASURING TESTING
Information Patent Application
TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL
- Publication number 20170115338
- Publication date Apr 27, 2017
- Sailendra Chadalavda
- G01 - MEASURING TESTING
Information Patent Application
DYNAMIC INDEPENDENT TEST PARTITION CLOCK
- Publication number 20170115351
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Pavan Kumar Datla Jagannadha
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR DYNAMIC TEST SYSTEMS AND METHODS
- Publication number 20170115353
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
SCAN SYSTEM INTERFACE (SSI) MODULE
- Publication number 20170115346
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...
- Publication number 20170115345
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Milind Sonawane
- G01 - MEASURING TESTING
Information Patent Application
INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...
- Publication number 20170115352
- Publication date Apr 27, 2017
- NVIDIA Corporation
- Dheepakkumaran Jayaraman
- G01 - MEASURING TESTING

Shantanu Sarangi

Person

Patents Grantslast 30 patents

Leveraging low power states for fault testing of processing cores a...

Techniques for testing semiconductor devices

In system test of chips in functional systems

Techniques for isolating interfaces while testing semiconductor dev...

In-system test of chips in functional systems

Performing testing utilizing staggered clocks

Leveraging low power states for fault testing of processing cores a...

Controlling test networks of chips using integrated processors

Hardware-controlled updating of a physical operating parameter for...

In system test of chips in functional systems

Leveraging low power states for fault testing of processing cores a...

On-chip execution of in-system test utilizing a generalized test image

Field adaptable in-system test mechanisms

Method and apparatus to access high volume test data over high spee...

Granular dynamic test systems and methods

Granular dynamic test systems and methods

Dynamic independent test partition clock

Method and system for dynamic standard test access (DSTA) for a log...

Independent test partition clock coordination across multiple test...

Scan system interface (SSI) module

Test partition external input/output interface control for test par...

Patents Applicationslast 30 patents

IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...

ASYNCHRONOUS IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

ASYNCHRONOUS IN-SYSTEM TESTING FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

TECHNIQUE FOR ENABLING ON-DIE NOISE MEASUREMENT DURING ATE TESTING...

LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...

PERFORMING TESTING UTILIZING STAGGERED CLOCKS

IN-SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

RUNTIME IN-SYSTEM TESTING

CONTROLLING TEST NETWORKS OF CHIPS USING INTEGRATED PROCESSORS

TECHNIQUES FOR ISOLATING INTERFACES WHILE TESTING SEMICONDUCTOR DEV...

TECHNIQUES FOR TESTING SEMICONDUCTOR DEVICES

LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...

HARDWARE-CONTROLLED UPDATING OF A PHYSICAL OPERATING PARAMETER FOR...

LEVERAGING LOW POWER STATES FOR FAULT TESTING OF PROCESSING CORES A...

ON-CHIP EXECUTION OF IN-SYSTEM TEST UTILIZING A GENERALIZED TEST IMAGE

IN SYSTEM TEST OF CHIPS IN FUNCTIONAL SYSTEMS

METHOD AND APPARATUS TO ACCESS HIGH VOLUME TEST DATA OVER HIGH SPEE...

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

TEST PARTITION EXTERNAL INPUT/OUTPUT INTERFACE CONTROL

DYNAMIC INDEPENDENT TEST PARTITION CLOCK

GRANULAR DYNAMIC TEST SYSTEMS AND METHODS

SCAN SYSTEM INTERFACE (SSI) MODULE

METHOD AND SYSTEM FOR DYNAMIC STANDARD TEST ACCESS (DSTA) FOR A LOG...

INDEPENDENT TEST PARTITION CLOCK COORDINATION ACROSS MULTIPLE TEST...