SHAOFENG YU

Person

PLANO, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
MOSFET with source side only stress
- Patent number 9,412,869
- Issue date Aug 9, 2016
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for changing crystal orientation in hybrid orien...
- Patent number 9,123,570
- Issue date Sep 1, 2015
- Texas Instruments Incorporated
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS process to improve SRAM yield
- Patent number 9,093,315
- Issue date Jul 28, 2015
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for facilitating the simultaneous silicidation of a polys...
- Patent number 9,035,399
- Issue date May 19, 2015
- Texas Instruments Incorporated
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOSFET with source side only stress
- Patent number 8,928,047
- Issue date Jan 6, 2015
- Texas Instruments Incorporated
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS process to improve SRAM yield
- Patent number 8,603,875
- Issue date Dec 10, 2013
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming fully silicided NMOS and PMOS semiconductor devic...
- Patent number 8,574,980
- Issue date Nov 5, 2013
- Texas Instruments Incorporated
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for changing crystal orientation in hybrid orien...
- Patent number 8,558,318
- Issue date Oct 15, 2013
- Texas Instruments Incorporated
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric static random access memory cell with dual stress liner
- Patent number 8,467,233
- Issue date Jun 18, 2013
- Texas Instruments Incorporated
- Shaofeng Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Low cost transistors using gate orientation and optimized implants
- Patent number 8,405,154
- Issue date Mar 26, 2013
- Texas Instruments Incorporated
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate dielectric first replacement gate processes and integrated cir...
- Patent number 8,372,703
- Issue date Feb 12, 2013
- Texas Instruments Incorporated
- Brian K. Kirkpatrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor gate electrode having conductor material layer
- Patent number 8,237,234
- Issue date Aug 7, 2012
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for integration of replacement gate in CMOS flow
- Patent number 8,062,966
- Issue date Nov 22, 2011
- Texas Instruments Incorporated
- Freido Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low cost transistors using gate orientation and optimized implants
- Patent number 7,994,009
- Issue date Aug 9, 2011
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor gate electrode having conductor material layer
- Patent number 7,968,957
- Issue date Jun 28, 2011
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective wet etch process for CMOS ICs having embedded strain indu...
- Patent number 7,943,456
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for changing crystal orientation in hybrid orien...
- Patent number 7,892,908
- Issue date Feb 22, 2011
- Texas Instruments Incorporated
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor gate electrode having conductor material layer
- Patent number 7,871,916
- Issue date Jan 18, 2011
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Border region defect reduction in hybrid orientation technology (HO...
- Patent number 7,855,111
- Issue date Dec 21, 2010
- Texas Instruments Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate dielectric first replacement gate processes and integrated cir...
- Patent number 7,838,356
- Issue date Nov 23, 2010
- Texas Instruments Incorporated
- Brian K. Kirkpatrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming source and drain regions utilizing dual capping l...
- Patent number 7,785,970
- Issue date Aug 31, 2010
- Texas Instruments Incorporated
- Frank Scott Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of simultaneously siliciding a polysilicon gate and source/d...
- Patent number 7,727,842
- Issue date Jun 1, 2010
- Texas Instruments Incorporated
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming silicided gates using buried metal layers
- Patent number 7,687,396
- Issue date Mar 30, 2010
- Texas Instruments Incorporated
- Steven Arthur Vitale
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor gate electrode having conductor material layer
- Patent number 7,642,610
- Issue date Jan 5, 2010
- Intel Corporation
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a fully silicided semiconductor device with indep...
- Patent number 7,585,738
- Issue date Sep 8, 2009
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of enhancing drive current in a transistor
- Patent number 7,547,596
- Issue date Jun 16, 2009
- Texas Instruments Incorporated
- Mark R. Visokay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual poly deposition and through gate oxide implants
- Patent number 7,435,638
- Issue date Oct 14, 2008
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of transistors with a fully silicided gate electrode an...
- Patent number 7,416,949
- Issue date Aug 26, 2008
- Texas Instruments Incorporated
- Michael Francis Pas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to obtain fully silicided poly gate
- Patent number 7,396,716
- Issue date Jul 8, 2008
- Texas Instruments Incorporated
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a silicided gate electrode using a buffer...
- Patent number 7,341,933
- Issue date Mar 11, 2008
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20150087127
- Publication date Mar 26, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS Process To Improve SRAM Yield
- Publication number 20140346609
- Publication date Nov 27, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...
- Publication number 20130292780
- Publication date Nov 7, 2013
- Angelo PINTO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Asymmetric Static Random Access Memory Cell with Dual Stress Liner
- Publication number 20120307550
- Publication date Dec 6, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- G11 - INFORMATION STORAGE
Information Patent Application
MOSFET WITH SOURCE SIDE ONLY STRESS
- Publication number 20120146054
- Publication date Jun 14, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Samuel Zafar Nawaz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS PROCESS TO IMPROVE SRAM YIELD
- Publication number 20120104510
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS
- Publication number 20110248347
- Publication date Oct 13, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Kamel BENAISSA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
- Publication number 20110186912
- Publication date Aug 4, 2011
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...
- Publication number 20110108893
- Publication date May 12, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIR...
- Publication number 20110031557
- Publication date Feb 10, 2011
- TEXAS INSTRUMENTS INCORPORATED
- BRIAN K. KIRKPATRICK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
- Publication number 20110018031
- Publication date Jan 27, 2011
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS
- Publication number 20100327374
- Publication date Dec 30, 2010
- Kamel Benaissa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST SYMMETRIC TRANSISTORS
- Publication number 20100327361
- Publication date Dec 30, 2010
- KAMEL BENAISSA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/D...
- Publication number 20100176462
- Publication date Jul 15, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIR...
- Publication number 20100164006
- Publication date Jul 1, 2010
- Texas Instruments Inc.
- BRIAN K. KIRKPATRICK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS
- Publication number 20100167472
- Publication date Jul 1, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Yiming Gu
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW
- Publication number 20100164008
- Publication date Jul 1, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE WET ETCH PROCESS FOR CMOS ICS HAVING EMBEDDED STRAIN INDU...
- Publication number 20100164005
- Publication date Jul 1, 2010
- TEXAS INSTRUMENTS INCORPORATED
- SHAOFENG YU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HO...
- Publication number 20100032727
- Publication date Feb 11, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devic...
- Publication number 20090321846
- Publication date Dec 31, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER
- Publication number 20090315076
- Publication date Dec 24, 2009
- Anand Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...
- Publication number 20090159933
- Publication date Jun 25, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Angelo Pinto
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING FULLY SILICIDED NMOS AND PMOS SEMICONDUCTOR DEVIC...
- Publication number 20090057776
- Publication date Mar 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Freidoon Mehrad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR DE-INTERLACING VIDEO DATA
- Publication number 20090053865
- Publication date Feb 26, 2009
- Frank Scott Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF ENHANCING DRIVE CURRENT IN A TRANSISTOR
- Publication number 20090032877
- Publication date Feb 5, 2009
- Texas Instruments Incorporated
- Mark R. Visokay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT...
- Publication number 20090020791
- Publication date Jan 22, 2009
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS
- Publication number 20080315328
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AN...
- Publication number 20080283941
- Publication date Nov 20, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Michael Francis Pas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEP...
- Publication number 20080265420
- Publication date Oct 30, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming a Fully Silicided Semiconductor Device with Indep...
- Publication number 20080265345
- Publication date Oct 30, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS

SHAOFENG YU

Person

Patents Grantslast 30 patents

MOSFET with source side only stress

Integration scheme for changing crystal orientation in hybrid orien...

CMOS process to improve SRAM yield

Structure for facilitating the simultaneous silicidation of a polys...

MOSFET with source side only stress

CMOS process to improve SRAM yield

Method of forming fully silicided NMOS and PMOS semiconductor devic...

Integration scheme for changing crystal orientation in hybrid orien...

Asymmetric static random access memory cell with dual stress liner

Low cost transistors using gate orientation and optimized implants

Gate dielectric first replacement gate processes and integrated cir...

Transistor gate electrode having conductor material layer

Method for integration of replacement gate in CMOS flow

Low cost transistors using gate orientation and optimized implants

Transistor gate electrode having conductor material layer

Selective wet etch process for CMOS ICs having embedded strain indu...

Integration scheme for changing crystal orientation in hybrid orien...

Transistor gate electrode having conductor material layer

Border region defect reduction in hybrid orientation technology (HO...

Gate dielectric first replacement gate processes and integrated cir...

Method of forming source and drain regions utilizing dual capping l...

Method of simultaneously siliciding a polysilicon gate and source/d...

Method of forming silicided gates using buried metal layers

Transistor gate electrode having conductor material layer

Method of forming a fully silicided semiconductor device with indep...

Method of enhancing drive current in a transistor

Dual poly deposition and through gate oxide implants

Fabrication of transistors with a fully silicided gate electrode an...

Method to obtain fully silicided poly gate

Method for manufacturing a silicided gate electrode using a buffer...

Patents Applicationslast 30 patents

MOSFET WITH SOURCE SIDE ONLY STRESS

CMOS Process To Improve SRAM Yield

INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...

Asymmetric Static Random Access Memory Cell with Dual Stress Liner

MOSFET WITH SOURCE SIDE ONLY STRESS

CMOS PROCESS TO IMPROVE SRAM YIELD

LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS

TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER

INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...

GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIR...

TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER

LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS

LOW COST SYMMETRIC TRANSISTORS

METHOD OF SIMULTANEOUSLY SILICIDING A POLYSILICON GATE AND SOURCE/D...

GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIR...

IMPLANTATION SHADOWING EFFECT REDUCTION USING THERMAL BAKE PROCESS

METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW

SELECTIVE WET ETCH PROCESS FOR CMOS ICS HAVING EMBEDDED STRAIN INDU...

BORDER REGION DEFECT REDUCTION IN HYBRID ORIENTATION TECHNOLOGY (HO...

Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devic...

TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER

INTEGRATION SCHEME FOR CHANGING CRYSTAL ORIENTATION IN HYBRID ORIEN...

METHOD OF FORMING FULLY SILICIDED NMOS AND PMOS SEMICONDUCTOR DEVIC...

METHOD AND APPARATUS FOR DE-INTERLACING VIDEO DATA

METHOD OF ENHANCING DRIVE CURRENT IN A TRANSISTOR

PROCESS METHOD TO FABRICATE CMOS CIRCUITS WITH DUAL STRESS CONTACT...

DUAL POLY DEPOSITION AND THROUGH GATE OXIDE IMPLANTS

FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AN...

METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEP...

Method of Forming a Fully Silicided Semiconductor Device with Indep...