Sharmin Sadoughi

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Calibrating device performance within an integrated circuit
- Patent number 8,653,844
- Issue date Feb 18, 2014
- Xilinx, Inc.
- Sharmin Sadoughi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of product performance improvement by selective feature sizi...
- Patent number 8,302,064
- Issue date Oct 30, 2012
- Xilinx, Inc.
- Sharmin Sadoughi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device with stress reduction layer
- Patent number 8,183,105
- Issue date May 22, 2012
- Xilinx, Inc.
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with stress reduction layer
- Patent number 8,035,166
- Issue date Oct 11, 2011
- Xilinx, Inc.
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for improving negative bias temperature instability (NBT...
- Patent number 7,629,653
- Issue date Dec 8, 2009
- Cypress Semiconductor Corporation
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for improving negative bias temperature instability (NBT...
- Patent number 7,256,087
- Issue date Aug 14, 2007
- Cypress Semiconductor Corporation
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having alignment marks with shallow trench...
- Patent number 7,192,839
- Issue date Mar 20, 2007
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In situ deposition of a nitride layer and of an anti-reflective layer
- Patent number 6,841,491
- Issue date Jan 11, 2005
- Cypress Semiconductor Corporation
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having alignment marks with shallow trench...
- Patent number 6,774,452
- Issue date Aug 10, 2004
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless contact architecture
- Patent number 6,713,831
- Issue date Mar 30, 2004
- Cypress Semiconductor Corp.
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and structure for isolating integrated circuit components an...
- Patent number 6,399,462
- Issue date Jun 4, 2002
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation scheme based on recessed locos using a sloped Si etch and...
- Patent number 6,033,991
- Issue date Mar 7, 2000
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT
- Publication number 20120229203
- Publication date Sep 13, 2012
- Xilinx, Inc.
- Sharmin Sadoughi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER
- Publication number 20120007188
- Publication date Jan 12, 2012
- Xilinx, Inc.
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER
- Publication number 20100258877
- Publication date Oct 14, 2010
- Xilinx, Inc.
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS

Sharmin Sadoughi

Person

Patents Grantslast 30 patents

Calibrating device performance within an integrated circuit

Method of product performance improvement by selective feature sizi...

Integrated circuit device with stress reduction layer

Integrated circuit device with stress reduction layer

Techniques for improving negative bias temperature instability (NBT...

Techniques for improving negative bias temperature instability (NBT...

Semiconductor structure having alignment marks with shallow trench...

In situ deposition of a nitride layer and of an anti-reflective layer

Semiconductor structure having alignment marks with shallow trench...

Borderless contact architecture

Method and structure for isolating integrated circuit components an...

Isolation scheme based on recessed locos using a sloped Si etch and...

Patents Applicationslast 30 patents

CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT

INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER

INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER