Sharon Levin

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming high-voltage silicon-on-insulator device with dio...
- Patent number 10,522,388
- Issue date Dec 31, 2019
- Tower Semiconductor Ltd.
- Einat Ophir Arad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus of a metal-oxide-semiconductor (MOS) transistor including...
- Patent number 10,217,826
- Issue date Feb 26, 2019
- Tower Semiconductor Ltd.
- Johnatan A. Kantarovsky
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor die with a metal via
- Patent number 9,837,411
- Issue date Dec 5, 2017
- TOWER SEMICONDUCTORS LTD.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS device having a low angle sloped oxide
- Patent number 9,812,566
- Issue date Nov 7, 2017
- TOWER SEMICONDUCTORS LTD.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double-resurf LDMOS with drift and PSURF implants self-aligned to a...
- Patent number 9,806,174
- Issue date Oct 31, 2017
- Tower Semiconductor Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep silicon via as a drain sinker in integrated vertical DMOS tran...
- Patent number 9,728,632
- Issue date Aug 8, 2017
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die including a high voltage capacitor
- Patent number 9,640,607
- Issue date May 2, 2017
- Tower Semiconductor Ltd.
- Sharon Levin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double-resurf LDMOS with drift and PSURF implants self-aligned to a...
- Patent number 9,484,454
- Issue date Nov 1, 2016
- Tower Semiconductor Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die including a Schottky diode
- Patent number 9,461,039
- Issue date Oct 4, 2016
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDMOS transistor having elevated field oxide bumps and method of ma...
- Patent number 9,330,979
- Issue date May 3, 2016
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double RESURF LDMOS with separately patterned P+ and N+ buried lay...
- Patent number 9,105,712
- Issue date Aug 11, 2015
- Tower Semiconductors Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep silicon via as a drain sinker in integrated vertical DMOS tran...
- Patent number 8,921,173
- Issue date Dec 30, 2014
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned LDMOS fabrication method integrated deep-sub-micron VL...
- Patent number 7,575,977
- Issue date Aug 18, 2009
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate defined Schottky diode
- Patent number 7,544,557
- Issue date Jun 9, 2009
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cobalt silicide schottky diode on isolated well
- Patent number 7,485,941
- Issue date Feb 3, 2009
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low parasitic capacitance Schottky diode
- Patent number 7,368,760
- Issue date May 6, 2008
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
- Publication number 20210320204
- Publication date Oct 14, 2021
- TOWER PARTNERS SEMICONDUCTOR CO., LTD.
- Masao SHINDO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS OF A METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR INCLUDING...
- Publication number 20180145139
- Publication date May 24, 2018
- Tower Semiconductor Ltd.
- Johnatan A. Kantarovsky
- G05 - CONTROLLING REGULATING
Information Patent Application
SEMICONDUCTOR DIE WITH A METAL VIA
- Publication number 20170018503
- Publication date Jan 19, 2017
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-RESURF LDMOS WITH DRIFT AND PSURF IMPLANTS SELF-ALIGNED TO A...
- Publication number 20160372578
- Publication date Dec 22, 2016
- Tower Semiconductor Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE INCLUDING A HIGH VOLTAGE CAPACITOR
- Publication number 20160260796
- Publication date Sep 8, 2016
- Tower Semiconductor Ltd.
- Sharon Levin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE INCLUDING A SCHOTTKY DIODE
- Publication number 20160240529
- Publication date Aug 18, 2016
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A...
- Publication number 20150279969
- Publication date Oct 1, 2015
- Tower Semiconductor Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Tran...
- Publication number 20150123194
- Publication date May 7, 2015
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A...
- Publication number 20140070315
- Publication date Mar 13, 2014
- Tower Semiconductor Ltd.
- Sagy Levy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Tran...
- Publication number 20130320443
- Publication date Dec 5, 2013
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Ma...
- Publication number 20100102388
- Publication date Apr 29, 2010
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-Aligned LDMOS Fabrication Method Integrated Deep-Sub-Micron VL...
- Publication number 20080242033
- Publication date Oct 2, 2008
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate defined schottky diode
- Publication number 20060125019
- Publication date Jun 15, 2006
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low parasitic capacitance schottky diode
- Publication number 20060125039
- Publication date Jun 15, 2006
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Cobalt silicide schottky diode on isolated well
- Publication number 20060125040
- Publication date Jun 15, 2006
- Tower Semiconductor Ltd.
- Sharon Levin
- H01 - BASIC ELECTRIC ELEMENTS

Sharon Levin

Person

Patents Grantslast 30 patents

Method of forming high-voltage silicon-on-insulator device with dio...

Apparatus of a metal-oxide-semiconductor (MOS) transistor including...

Semiconductor die with a metal via

LDMOS device having a low angle sloped oxide

Double-resurf LDMOS with drift and PSURF implants self-aligned to a...

Deep silicon via as a drain sinker in integrated vertical DMOS tran...

Die including a high voltage capacitor

Double-resurf LDMOS with drift and PSURF implants self-aligned to a...

Die including a Schottky diode

LDMOS transistor having elevated field oxide bumps and method of ma...

Double RESURF LDMOS with separately patterned P+ and N+ buried lay...

Deep silicon via as a drain sinker in integrated vertical DMOS tran...

Self-aligned LDMOS fabrication method integrated deep-sub-micron VL...

Gate defined Schottky diode

Cobalt silicide schottky diode on isolated well

Low parasitic capacitance Schottky diode

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME

APPARATUS OF A METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR INCLUDING...

SEMICONDUCTOR DIE WITH A METAL VIA

DOUBLE-RESURF LDMOS WITH DRIFT AND PSURF IMPLANTS SELF-ALIGNED TO A...

DIE INCLUDING A HIGH VOLTAGE CAPACITOR

DIE INCLUDING A SCHOTTKY DIODE

Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A...

Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Tran...

Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A...

Deep Silicon Via As A Drain Sinker In Integrated Vertical DMOS Tran...

LDMOS Transistor Having Elevated Field Oxide Bumps And Method Of Ma...

Self-Aligned LDMOS Fabrication Method Integrated Deep-Sub-Micron VL...

Gate defined schottky diode

Low parasitic capacitance schottky diode

Cobalt silicide schottky diode on isolated well