Shawn Nikoukary

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods for avoiding parasitic capacitance in an integrated circuit...
- Patent number 8,288,269
- Issue date Oct 16, 2012
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Device for avoiding parasitic capacitance in an integrated circuit...
- Patent number 8,049,340
- Issue date Nov 1, 2011
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Device for minimizing differential pair length mismatch and impedan...
- Patent number 7,180,011
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Methods for Avoiding Parasitic Capacitance in an Integrated Circuit...
- Publication number 20120021599
- Publication date Jan 26, 2012
- LSI Corporation
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
DEVICE FOR AVOIDING PARASITIC CAPACITANCE IN AN INTEGRATED CIRCUIT...
- Publication number 20070222084
- Publication date Sep 27, 2007
- Jeffrey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR