Sheldon Aronowitz

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for creating barriers for copper diffusion
- Patent number 7,829,455
- Issue date Nov 9, 2010
- LSI Corporation
- Vladimir Zubkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of treating metal and metal salts to enable thin layer depos...
- Patent number 7,670,645
- Issue date Mar 2, 2010
- LSI Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of vaporizing and ionizing metals for use in semiconductor p...
- Patent number 7,323,228
- Issue date Jan 29, 2008
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method and apparatus for forming a memory structure having an elect...
- Patent number 7,132,336
- Issue date Nov 7, 2006
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for creating barriers for copper diffusion
- Patent number 7,115,991
- Issue date Oct 3, 2006
- LSI Logic Corporation
- Vladimir Zubkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vaporization and ionization of metals for use in semiconductor proc...
- Patent number 7,084,408
- Issue date Aug 1, 2006
- LSI Logic Corporation
- James Kimball
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for growing thin films
- Patent number 7,081,296
- Issue date Jul 25, 2006
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Low dielectric constant fluorine and carbon-containing silicon oxid...
- Patent number 7,015,168
- Issue date Mar 21, 2006
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Memory device having an electron trapping layer in a high-K dielect...
- Patent number 6,989,565
- Issue date Jan 24, 2006
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Calcium doped polysilicon gate electrodes
- Patent number 6,930,362
- Issue date Aug 16, 2005
- LSI Logic Corporation
- Mohammad R. Mirabedini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-K dielectric gate material uniquely formed
- Patent number 6,919,263
- Issue date Jul 19, 2005
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process to minimize polysilicon gate depletion and dopant penetrati...
- Patent number 6,897,102
- Issue date May 24, 2005
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a low dielectric constant fluorine and carbon-c...
- Patent number 6,858,195
- Issue date Feb 22, 2005
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Integrated circuit isolation system
- Patent number 6,831,348
- Issue date Dec 14, 2004
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of chemically altering a silicon surface and associated elec...
- Patent number 6,822,308
- Issue date Nov 23, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for etching a controllable thickness of oxide on an integra...
- Patent number 6,759,337
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned alloy capping layers for copper interconnect structures
- Patent number 6,747,358
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Paul Rissman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for growing thin films
- Patent number 6,743,474
- Issue date Jun 1, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for reticle formation utilizing metal vaporization
- Patent number 6,673,498
- Issue date Jan 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Process for forming a low dielectric constant fluorine and carbon-c...
- Patent number 6,649,219
- Issue date Nov 18, 2003
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of chemically altering a silicon surface and associated elec...
- Patent number 6,627,556
- Issue date Sep 30, 2003
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit isolation system
- Patent number 6,613,651
- Issue date Sep 2, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming a low dielectric constant fluorine and carbon c...
- Patent number 6,572,925
- Issue date Jun 3, 2003
- LSI Logic Corporation
- Vladimir Zubkov
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for creating self-aligned alloy capping layers for copper in...
- Patent number 6,566,262
- Issue date May 20, 2003
- LSI Logic Corporation
- Paul Rissman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for forming high dielectric constant gate dielectric for in...
- Patent number 6,511,925
- Issue date Jan 28, 2003
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...
- Patent number 6,413,881
- Issue date Jul 2, 2002
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of integrated circuit structure using one or more silicon...
- Patent number 6,331,468
- Issue date Dec 18, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant multiple carbon-containing silicon oxide di...
- Patent number 6,303,047
- Issue date Oct 16, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid surface/buried-channel MOSFET
- Patent number 6,246,093
- Issue date Jun 12, 2001
- LSI Logic Corporation
- Lindor E. Henrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FETs having lightly doped drain regions that are shaped with counte...
- Patent number 6,180,470
- Issue date Jan 30, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Memory device having an electron trapping layer in a high-K dielect...
- Publication number 20050258475
- Publication date Nov 24, 2005
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for creating barriers for copper diffusion
- Publication number 20050179138
- Publication date Aug 18, 2005
- LSI Logic Corporation
- Vladimir Zubkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low dielectric constant fluorine and carbon-containing silicon oxid...
- Publication number 20050098856
- Publication date May 12, 2005
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method for growing thin films
- Publication number 20040175947
- Publication date Sep 9, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method for creating barriers to metal contamination in silicon oxides
- Publication number 20040121550
- Publication date Jun 24, 2004
- Vladimir Zubkov
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process to minimize polysilicon gate depletion and dopant penetrati...
- Publication number 20040110328
- Publication date Jun 10, 2004
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High-K dielectric gate material uniquely formed
- Publication number 20040089887
- Publication date May 13, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method of chemically altering a silicon surface and associated elec...
- Publication number 20030235988
- Publication date Dec 25, 2003
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low dielectric constant fluorine and carbon-containing silicon oxid...
- Publication number 20030207750
- Publication date Nov 6, 2003
- Vladimir Zubkov
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Integrated circuit isolation system
- Publication number 20030162366
- Publication date Aug 28, 2003
- LSI Logic Corporation
- Helmut Puchner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for forming a low dielectric constant fluorine and carbon-c...
- Publication number 20020119315
- Publication date Aug 29, 2002
- Sheldon Aronowitz
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process for forming a low dielectric constant fluorine and carbon-c...
- Publication number 20020117082
- Publication date Aug 29, 2002
- Sheldon Aronowitz
- C01 - INORGANIC CHEMISTRY
Information Patent Application
Process for forming a low dielectric constant fluorine and carbon-c...
- Publication number 20020119326
- Publication date Aug 29, 2002
- Vladimir Zubkov
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Sheldon Aronowitz

Person

Patents Grantslast 30 patents

Method for creating barriers for copper diffusion

Method of treating metal and metal salts to enable thin layer depos...

Method of vaporizing and ionizing metals for use in semiconductor p...

Method and apparatus for forming a memory structure having an elect...

Method for creating barriers for copper diffusion

Vaporization and ionization of metals for use in semiconductor proc...

Method for growing thin films

Low dielectric constant fluorine and carbon-containing silicon oxid...

Memory device having an electron trapping layer in a high-K dielect...

Calcium doped polysilicon gate electrodes

High-K dielectric gate material uniquely formed

Process to minimize polysilicon gate depletion and dopant penetrati...

Process for forming a low dielectric constant fluorine and carbon-c...

Integrated circuit isolation system

Method of chemically altering a silicon surface and associated elec...

Process for etching a controllable thickness of oxide on an integra...

Self-aligned alloy capping layers for copper interconnect structures

Method for growing thin films

Method for reticle formation utilizing metal vaporization

Process for forming a low dielectric constant fluorine and carbon-c...

Method of chemically altering a silicon surface and associated elec...

Integrated circuit isolation system

Process for forming a low dielectric constant fluorine and carbon c...

Method for creating self-aligned alloy capping layers for copper in...

Process for forming high dielectric constant gate dielectric for in...

PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...

Formation of integrated circuit structure using one or more silicon...

Low dielectric constant multiple carbon-containing silicon oxide di...

Hybrid surface/buried-channel MOSFET

FETs having lightly doped drain regions that are shaped with counte...

Patents Applicationslast 30 patents

Memory device having an electron trapping layer in a high-K dielect...

Method for creating barriers for copper diffusion

Low dielectric constant fluorine and carbon-containing silicon oxid...

Method for growing thin films

Method for creating barriers to metal contamination in silicon oxides

Process to minimize polysilicon gate depletion and dopant penetrati...

High-K dielectric gate material uniquely formed

Method of chemically altering a silicon surface and associated elec...

Low dielectric constant fluorine and carbon-containing silicon oxid...

Integrated circuit isolation system

Process for forming a low dielectric constant fluorine and carbon-c...

Process for forming a low dielectric constant fluorine and carbon-c...

Process for forming a low dielectric constant fluorine and carbon-c...