Sheyang Ning

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Establishing bitline, wordline and boost voltages to manage a maxim...
- Patent number 12,347,485
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Level shifting in all levels programming of a memory device in a me...
- Patent number 12,260,914
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
In-line programming adjustment of a memory cell in a memory sub-system
- Patent number 12,254,927
- Issue date Mar 18, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
All level coarse/fine programming of memory cells
- Patent number 12,224,012
- Issue date Feb 11, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent slow-fast memory cell programming
- Patent number 12,211,552
- Issue date Jan 28, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing dielectric stress of a memory device using controlled ramp...
- Patent number 12,141,445
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for determining memory cell data states
- Patent number 12,112,819
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
In-line programming adjustment of a memory cell in a memory sub-system
- Patent number 12,014,778
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast bit erase for upper tail tightening of threshold voltage distr...
- Patent number 11,961,566
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices with four data line bias levels
- Patent number 11,915,758
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
All levels programming of a memory device in a memory sub-system
- Patent number 11,887,668
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for determining memory cell data states
- Patent number 11,798,647
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Overwrite mode in memory programming operations
- Patent number 11,749,346
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Tomoko Ogura Iwasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing maximum programming voltage in memory programming operations
- Patent number 11,742,036
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Intervallic dynamic start voltage and program verify sampling in a...
- Patent number 11,664,079
- Issue date May 30, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices with four data line bias levels
- Patent number 11,562,791
- Issue date Jan 24, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing dielectric stress of a memory device using controlled ramp...
- Patent number 11,494,084
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intervallic dynamic start voltage and program verify sampling in a...
- Patent number 11,462,281
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...
- Publication number 20250191659
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS
- Publication number 20250149093
- Publication date May 8, 2025
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
VECTOR ELEMENT MULTIPLICATION IN NAND MEMORY
- Publication number 20250124102
- Publication date Apr 17, 2025
- Micron Technology, Inc.
- Dmitri Yudanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT...
- Publication number 20240339158
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM VOLTAGE SELECTION DURING ALL LEVELS PROGRAMMING OF A MEMORY...
- Publication number 20240295970
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM
- Publication number 20240290389
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTR...
- Publication number 20240221841
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
VOLATILE DATA STORAGE IN NAND MEMORY
- Publication number 20240177755
- Publication date May 30, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR DETERMINING MEMORY CELL DATA STATES
- Publication number 20240029809
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
ESTABLISHING BITLINE, WORDLINE AND BOOST VOLTAGES TO MANAGE A MAXIM...
- Publication number 20240005987
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
- Publication number 20230397401
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS
- Publication number 20230317171
- Publication date Oct 5, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT SLOW-FAST MEMORY CELL PROGRAMMING
- Publication number 20230307055
- Publication date Sep 28, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES
- Publication number 20230274786
- Publication date Aug 31, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE
- Publication number 20230207019
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE LOSS ACCELERATION DURING PROGRAMMING OF MEMORY CELLS IN A ME...
- Publication number 20230207018
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
- Publication number 20230162793
- Publication date May 25, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
TIME INTERVALS AMONG MEMORY OPERATIONS OF NON-VOLATILE MEMORY
- Publication number 20230068482
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS
- Publication number 20230039026
- Publication date Feb 9, 2023
- Micron Technology, Inc.
- Hao T. Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTR...
- Publication number 20230034752
- Publication date Feb 2, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DIELECTRIC STRESS OF A MEMORY DEVICE USING CONTROLLED RAMP...
- Publication number 20230026558
- Publication date Jan 26, 2023
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERVALLIC DYNAMIC START VOLTAGE AND PROGRAM VERIFY SAMPLING IN A...
- Publication number 20230005553
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
OVERWRITE MODE IN MEMORY PROGRAMMING OPERATIONS
- Publication number 20220375525
- Publication date Nov 24, 2022
- Micron Technology, Inc.
- Tomoko Ogura Iwasaki
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING MAXIMUM PROGRAMMING VOLTAGE IN MEMORY PROGRAMMING OPERATIONS
- Publication number 20220351789
- Publication date Nov 3, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM
- Publication number 20220310166
- Publication date Sep 29, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...
- Publication number 20220310167
- Publication date Sep 29, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM
- Publication number 20220310165
- Publication date Sep 29, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DIELECTRIC STRESS OF A MEMORY DEVICE USING CONTROLLED RAMP...
- Publication number 20220187995
- Publication date Jun 16, 2022
- Micron Technology, Inc.
- Sheyang Ning
- G06 - COMPUTING CALCULATING COUNTING

Sheyang Ning

Person

Patents Grantslast 30 patents

Establishing bitline, wordline and boost voltages to manage a maxim...

Level shifting in all levels programming of a memory device in a me...

In-line programming adjustment of a memory cell in a memory sub-system

All level coarse/fine programming of memory cells

Concurrent slow-fast memory cell programming

Managing dielectric stress of a memory device using controlled ramp...

Apparatus for determining memory cell data states

In-line programming adjustment of a memory cell in a memory sub-system

Fast bit erase for upper tail tightening of threshold voltage distr...

Memory devices with four data line bias levels

All levels programming of a memory device in a memory sub-system

Apparatus and methods for determining memory cell data states

Overwrite mode in memory programming operations

Reducing maximum programming voltage in memory programming operations

Intervallic dynamic start voltage and program verify sampling in a...

Memory devices with four data line bias levels

Managing dielectric stress of a memory device using controlled ramp...

Intervallic dynamic start voltage and program verify sampling in a...

Patents Applicationslast 30 patents

LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...

ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS

VECTOR ELEMENT MULTIPLICATION IN NAND MEMORY

CONTROLLING PILLAR VOLTAGE USING WORDLINE BOOST VOLTAGE AND SELECT...

PROGRAM VOLTAGE SELECTION DURING ALL LEVELS PROGRAMMING OF A MEMORY...

IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM

FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTR...

VOLATILE DATA STORAGE IN NAND MEMORY

APPARATUS FOR DETERMINING MEMORY CELL DATA STATES

ESTABLISHING BITLINE, WORDLINE AND BOOST VOLTAGES TO MANAGE A MAXIM...

MEMORY CELL CAPACITOR STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS

ALL LEVEL COARSE/FINE PROGRAMMING OF MEMORY CELLS

CONCURRENT SLOW-FAST MEMORY CELL PROGRAMMING

APPARATUS AND METHODS FOR DETERMINING MEMORY CELL DATA STATES

MULTI-LEVEL CELL AND MULTI-SUB-BLOCK PROGRAMMING IN A MEMORY DEVICE

CHARGE LOSS ACCELERATION DURING PROGRAMMING OF MEMORY CELLS IN A ME...

MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS

TIME INTERVALS AMONG MEMORY OPERATIONS OF NON-VOLATILE MEMORY

MEMORY DEVICES WITH FOUR DATA LINE BIAS LEVELS

FAST BIT ERASE FOR UPPER TAIL TIGHTENING OF THRESHOLD VOLTAGE DISTR...

MANAGING DIELECTRIC STRESS OF A MEMORY DEVICE USING CONTROLLED RAMP...

INTERVALLIC DYNAMIC START VOLTAGE AND PROGRAM VERIFY SAMPLING IN A...

OVERWRITE MODE IN MEMORY PROGRAMMING OPERATIONS

REDUCING MAXIMUM PROGRAMMING VOLTAGE IN MEMORY PROGRAMMING OPERATIONS

IN-LINE PROGRAMMING ADJUSTMENT OF A MEMORY CELL IN A MEMORY SUB-SYSTEM

LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...

ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A MEMORY SUB-SYSTEM

MANAGING DIELECTRIC STRESS OF A MEMORY DEVICE USING CONTROLLED RAMP...