Shiba Narayan Mohanty

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Memory with high-speed and area-efficient read path
- Patent number 11,315,609
- Issue date Apr 26, 2022
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power and high-density core-power lowering for memory write assist
- Patent number 11,074,967
- Issue date Jul 27, 2021
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G05 - CONTROLLING REGULATING
Information Patent Grant
Clock buffering to reduce memory hold time
- Patent number 10,901,454
- Issue date Jan 26, 2021
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory with high-speed and area-efficient read path
- Patent number 10,854,246
- Issue date Dec 1, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory core power-up with reduced peak current
- Patent number 10,839,866
- Issue date Nov 17, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power and high-density core-power lowering for memory write assist
- Patent number 10,832,764
- Issue date Nov 10, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G05 - CONTROLLING REGULATING
Information Patent Grant
SRAM write yield enhancement with pull-up strength modulation
- Patent number 10,811,086
- Issue date Oct 20, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Boost generation circuitry for memory
- Patent number 10,614,865
- Issue date Apr 7, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE
Information Patent Grant
Robust write driver scheme for static random access memory compilers
- Patent number 10,147,483
- Issue date Dec 4, 2018
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH
- Publication number 20210020206
- Publication date Jan 21, 2021
- Qualcomm Incorporated
- Adithya BHASKARAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
- Publication number 20210020234
- Publication date Jan 21, 2021
- Qualcomm Incorporated
- Adithya BHASKARAN
- G05 - CONTROLLING REGULATING
Information Patent Application
MEMORY CORE POWER-UP WITH REDUCED PEAK CURRENT
- Publication number 20200381023
- Publication date Dec 3, 2020
- QUALCOMM Incorporated
- Shiba Narayan MOHANTY
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with High-Speed and Area-Efficient Read Path
- Publication number 20200372939
- Publication date Nov 26, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK BUFFERING TO REDUCE MEMORY HOLD TIME
- Publication number 20200249716
- Publication date Aug 6, 2020
- QUALCOMM Incorporated
- Shiba Narayan Mohanty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST
- Publication number 20200251163
- Publication date Aug 6, 2020
- QUALCOMM Incorporated
- Adithya Bhaskaran
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST GENERATION CIRCUITRY FOR MEMORY
- Publication number 20200126604
- Publication date Apr 23, 2020
- QUALCOMM Incorporated
- Shiba Narayan MOHANTY
- G11 - INFORMATION STORAGE

Shiba Narayan Mohanty

Person

Patents Grantslast 30 patents

Memory with high-speed and area-efficient read path

Low-power and high-density core-power lowering for memory write assist

Clock buffering to reduce memory hold time

Memory with high-speed and area-efficient read path

Memory core power-up with reduced peak current

Low-power and high-density core-power lowering for memory write assist

SRAM write yield enhancement with pull-up strength modulation

Boost generation circuitry for memory

Robust write driver scheme for static random access memory compilers

Patents Applicationslast 30 patents

MEMORY WITH HIGH-SPEED AND AREA-EFFICIENT READ PATH

LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST

MEMORY CORE POWER-UP WITH REDUCED PEAK CURRENT

Memory with High-Speed and Area-Efficient Read Path

CLOCK BUFFERING TO REDUCE MEMORY HOLD TIME

LOW-POWER AND HIGH-DENSITY CORE-POWER LOWERING FOR MEMORY WRITE ASSIST

BOOST GENERATION CIRCUITRY FOR MEMORY