Shinichi Iketani

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming a laminate structure having a plated through-hole...
- Patent number 12,150,254
- Issue date Nov 19, 2024
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Catalyzed metal foil and uses thereof to produce electrical circuits
- Patent number 12,063,748
- Issue date Aug 13, 2024
- AVERATEK CORPORATION
- Shinichi Iketani
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Catalyzed metal foil and uses thereof
- Patent number 11,877,404
- Issue date Jan 16, 2024
- AVERATEK CORPORATION
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 11,765,827
- Issue date Sep 19, 2023
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Asymmetrical electrolytic plating for a conductive pattern
- Patent number 11,716,819
- Issue date Aug 1, 2023
- AVERATEK CORPORATION
- Michael Riley Vinson
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Coating of nano-scaled cavities
- Patent number 11,549,184
- Issue date Jan 10, 2023
- AVERATEK CORPORATION
- Sunity K. Sharma
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods of forming high aspect ratio plated through holes and high...
- Patent number 11,399,439
- Issue date Jul 26, 2022
- Sanmina Corporation
- Douglas Ward Thomas
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 11,304,311
- Issue date Apr 12, 2022
- Sanmina Corporation
- Shinichi Iketani
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Laminate structures with hole plugs and methods of forming laminate...
- Patent number 11,246,226
- Issue date Feb 8, 2022
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Coating of nano-scaled cavities
- Patent number 11,142,825
- Issue date Oct 12, 2021
- AVERATEK CORPORATION
- Sunity K. Sharma
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Three dimensional circuit formation
- Patent number 11,076,492
- Issue date Jul 27, 2021
- AVERATEK CORPORATION
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of manufacturing ultra thin dielectric printed circuit boar...
- Patent number 10,993,333
- Issue date Apr 27, 2021
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 10,820,427
- Issue date Oct 27, 2020
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer printed circuit board via hole registration and accuracy
- Patent number 10,811,210
- Issue date Oct 20, 2020
- Sanmina Corporation
- Shinichi Iketani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a laminate structure having a plated through-hole...
- Patent number 10,757,819
- Issue date Aug 25, 2020
- Sanmina Corporation
- Shinichi Iketani
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 10,667,390
- Issue date May 26, 2020
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer printed circuit board via hole registration and accuracy
- Patent number 10,446,356
- Issue date Oct 15, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 10,362,687
- Issue date Jul 23, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for forming hole plug
- Patent number 10,237,983
- Issue date Mar 19, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of forming blind vias for printed circuit boards
- Patent number 10,201,085
- Issue date Feb 5, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of forming high aspect ratio plated through holes and high...
- Patent number 10,188,001
- Issue date Jan 22, 2019
- Sanmina Corporation
- Douglas Ward Thomas
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 10,123,432
- Issue date Nov 6, 2018
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 9,781,830
- Issue date Oct 3, 2017
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Simultaneous and selective wide gap partitioning of via structures...
- Patent number 9,781,844
- Issue date Oct 3, 2017
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of segmented through hole formation using dual diameter thr...
- Patent number 9,661,758
- Issue date May 23, 2017
- Sanmina Corporation
- Douglas Ward Thomas
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Catalyzed Metal Foil and Uses Thereof
- Publication number 20240407106
- Publication date Dec 5, 2024
- Averatek Corporation
- Shinichi Iketani
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
ASYMMETRICAL ELECTROLYTIC PLATING FOR A CONDUCTIVE PATTERN
- Publication number 20230345642
- Publication date Oct 26, 2023
- Averatek Corporation
- Michael Riley Vinson
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
SYSTEMS AND METHODS FOR MANUFACTURING
- Publication number 20220418113
- Publication date Dec 29, 2022
- Averatek Corporation
- Michael Riley Vinson
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHODS OF FORMING HIGH ASPECT RATIO PLATED THROUGH HOLES AND HIGH...
- Publication number 20220338355
- Publication date Oct 20, 2022
- Sanmina Corporation
- Douglas Ward THOMAS
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Methods and Devices for High Resistance and Low Resistance Conducto...
- Publication number 20220319741
- Publication date Oct 6, 2022
- Averatek Corporation
- Shinichi IKETANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COATING OF NANO-SCALED CAVITIES
- Publication number 20220025520
- Publication date Jan 27, 2022
- Averatek Corporation
- Sunity K. SHARMA
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
THREE DIMENSIONAL CIRCUIT FORMATION
- Publication number 20210345498
- Publication date Nov 4, 2021
- Averatek Corporation
- Shinichi IKETANI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEMS AND METHODS FOR MANUFACTURING
- Publication number 20210307177
- Publication date Sep 30, 2021
- Averatek Corporation
- Shinichi Iketani
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
CATALYZED METAL FOIL AND USES THEREOF
- Publication number 20210259112
- Publication date Aug 19, 2021
- Averatek Corporation
- Shinichi IKETANI
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
CATALYZED METAL FOIL AND USES THEREOF
- Publication number 20210259115
- Publication date Aug 19, 2021
- Averatek Corporation
- Shinichi IKETANI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AN...
- Publication number 20210243903
- Publication date Aug 5, 2021
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20210153360
- Publication date May 20, 2021
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SYSTEMS AND METHODS FOR MANUFACTURING
- Publication number 20210045252
- Publication date Feb 11, 2021
- Averatek Corporation
- Haris BASIT
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHOD OF FORMING A LAMINATE STRUCTURE HAVING A PLATED THROUGH-HOLE...
- Publication number 20210014980
- Publication date Jan 14, 2021
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20200383204
- Publication date Dec 3, 2020
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
COATING OF NANO-SCALED CAVITIES
- Publication number 20200248311
- Publication date Aug 6, 2020
- Averatek Corporation
- Sunity K. SHARMA
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PATTERN FORMATION USING CATALYST BLOCKER
- Publication number 20200232098
- Publication date Jul 23, 2020
- Averatek Corporation
- Michael Riley VINSON
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
NANO METAL FILM DEPOSITION
- Publication number 20200190670
- Publication date Jun 18, 2020
- Averatek Corporation
- Sunity K SHARMA
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
THREE DIMENSIONAL CIRCUIT FORMATION
- Publication number 20200196456
- Publication date Jun 18, 2020
- Averatek Corporation
- Shinichi IKETANI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY
- Publication number 20200043690
- Publication date Feb 6, 2020
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20200015364
- Publication date Jan 9, 2020
- Sanmina Corporation
- Shinichi Iketani
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
ASYMMETRICAL ELECTROLYTIC PLATING FOR A CONDUCTIVE PATTERN
- Publication number 20190394887
- Publication date Dec 26, 2019
- Averatek Corporation
- Michael Riley Vinson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PATTERNING OF ELECTROLESS METALS
- Publication number 20190394888
- Publication date Dec 26, 2019
- Averatek Corporation
- Shinichi Iketani
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
LAMINATE STRUCTURES WITH HOLE PLUGS AND METHODS OF FORMING LAMINATE...
- Publication number 20190208645
- Publication date Jul 4, 2019
- Sanmina Corporation
- Shinichi IKETANI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS OF FORMING HIGH ASPECT RATIO PLATED THROUGH HOLES AND HIGH...
- Publication number 20190159346
- Publication date May 23, 2019
- Sanmina Corporation
- Douglas Ward THOMAS
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...
- Publication number 20190075662
- Publication date Mar 7, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AN...
- Publication number 20190021177
- Publication date Jan 17, 2019
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS
- Publication number 20180317327
- Publication date Nov 1, 2018
- Sanmina Corporation
- Shinichi IKETANI
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
METHODS OF FORMING BLIND VIAS FOR PRINTED CIRCUIT BOARDS
- Publication number 20180279473
- Publication date Sep 27, 2018
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY
- Publication number 20180110133
- Publication date Apr 19, 2018
- Sanmina Corporation
- Shinichi Iketani
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Shinichi Iketani

Person

Patents Grantslast 30 patents

Method of forming a laminate structure having a plated through-hole...

Catalyzed metal foil and uses thereof to produce electrical circuits

Catalyzed metal foil and uses thereof

Simultaneous and selective wide gap partitioning of via structures...

Asymmetrical electrolytic plating for a conductive pattern

Coating of nano-scaled cavities

Methods of forming high aspect ratio plated through holes and high...

Simultaneous and selective wide gap partitioning of via structures...

Laminate structures with hole plugs and methods of forming laminate...

Coating of nano-scaled cavities

Three dimensional circuit formation

Methods of manufacturing ultra thin dielectric printed circuit boar...

Simultaneous and selective wide gap partitioning of via structures...

Multilayer printed circuit board via hole registration and accuracy

Method of forming a laminate structure having a plated through-hole...

Simultaneous and selective wide gap partitioning of via structures...

Multilayer printed circuit board via hole registration and accuracy

Simultaneous and selective wide gap partitioning of via structures...

Method for forming hole plug

Methods of forming blind vias for printed circuit boards

Methods of forming high aspect ratio plated through holes and high...

Simultaneous and selective wide gap partitioning of via structures...

Simultaneous and selective wide gap partitioning of via structures...

Simultaneous and selective wide gap partitioning of via structures...

Methods of segmented through hole formation using dual diameter thr...

Patents Applicationslast 30 patents

Catalyzed Metal Foil and Uses Thereof

ASYMMETRICAL ELECTROLYTIC PLATING FOR A CONDUCTIVE PATTERN

SYSTEMS AND METHODS FOR MANUFACTURING

METHODS OF FORMING HIGH ASPECT RATIO PLATED THROUGH HOLES AND HIGH...

Methods and Devices for High Resistance and Low Resistance Conducto...

COATING OF NANO-SCALED CAVITIES

THREE DIMENSIONAL CIRCUIT FORMATION

SYSTEMS AND METHODS FOR MANUFACTURING

CATALYZED METAL FOIL AND USES THEREOF

CATALYZED METAL FOIL AND USES THEREOF

ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AN...

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

SYSTEMS AND METHODS FOR MANUFACTURING

METHOD OF FORMING A LAMINATE STRUCTURE HAVING A PLATED THROUGH-HOLE...

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

COATING OF NANO-SCALED CAVITIES

PATTERN FORMATION USING CATALYST BLOCKER

NANO METAL FILM DEPOSITION

THREE DIMENSIONAL CIRCUIT FORMATION

MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

ASYMMETRICAL ELECTROLYTIC PLATING FOR A CONDUCTIVE PATTERN

PATTERNING OF ELECTROLESS METALS

LAMINATE STRUCTURES WITH HOLE PLUGS AND METHODS OF FORMING LAMINATE...

METHODS OF FORMING HIGH ASPECT RATIO PLATED THROUGH HOLES AND HIGH...

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES...

ULTRA THIN DIELECTRIC PRINTED CIRCUIT BOARDS WITH THIN LAMINATES AN...

METHODS OF FORMING SEGMENTED VIAS FOR PRINTED CIRCUIT BOARDS

METHODS OF FORMING BLIND VIAS FOR PRINTED CIRCUIT BOARDS

MULTILAYER PRINTED CIRCUIT BOARD VIA HOLE REGISTRATION AND ACCURACY