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Shinichi Inoue
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Satsuma, JP
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Patents Grants
last 30 patents
Information
Patent Grant
PLL circuit and frequency division method reducing spurious noise
Patent number
6,628,153
Issue date
Sep 30, 2003
Fujitsu Limited
Shinichi Inoue
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Voltage controlled oscillator using control transistors in a loop f...
Patent number
5,061,906
Issue date
Oct 29, 1991
Fujitsu Limited
Shinichi Inoue
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Method for producing MOS semiconductor device
Patent number
4,349,395
Issue date
Sep 14, 1982
Fujitsu Limited
Nobuo Toyokura
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Magnetically controlled switching device
Patent number
4,330,770
Issue date
May 18, 1982
Fujitsu Limited
Hirotaka Kashiwabara
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
MIS Device having a metal and insulating layer containing at least...
Patent number
4,270,136
Issue date
May 26, 1981
Fujitsu Limited
Nobuo Toyokura
H01 - BASIC ELECTRIC ELEMENTS
Patents Applications
last 30 patents
Information
Patent Application
PLL circuit and frequency division method reducing spurious noise
Publication number
20020070780
Publication date
Jun 13, 2002
FUJITSU LIMITED
Shinichi Inoue
H03 - BASIC ELECTRONIC CIRCUITRY