Shinji Fukasawa

Person

Kasugai-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Method for eliminating hold error in scan chain
- Patent number 7,480,844
- Issue date Jan 20, 2009
- Fujitsu Limited
- Shouji Sakuma
- G01 - MEASURING TESTING
Information Patent Grant
Layout method for semiconductor integrated circuit, layout program...
- Patent number 7,437,699
- Issue date Oct 14, 2008
- Fujitsu Limited
- Hirotaka Morita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for laying out cells in a semiconductor device
- Patent number 7,185,303
- Issue date Feb 27, 2007
- Fujitsu Limited
- Shinji Fukasawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device and layout data generation apparatus
- Patent number 6,941,534
- Issue date Sep 6, 2005
- Fujitsu Limited
- Shinji Fukasawa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method for eliminating hold error in scan chain
- Publication number 20060236177
- Publication date Oct 19, 2006
- FUJITSU LIMITED
- Shouji Sakuma
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for laying out cells in a semiconductor device
- Publication number 20060225016
- Publication date Oct 5, 2006
- FUJITSU LIMITED
- Shinji Fukasawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Layout method for semiconductor integrated circuit, layout program...
- Publication number 20060064663
- Publication date Mar 23, 2006
- FUJITSU LIMITED
- Hirotaka Morita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device having a multiple layer wiring structure, wiri...
- Publication number 20030067075
- Publication date Apr 10, 2003
- FUJITSU LIMITED
- Shinji Fukasawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a multiple layer wiring structure, wiri...
- Publication number 20030015800
- Publication date Jan 23, 2003
- FUJITSU LIMITED
- Shinji Fukasawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having a multiple layer wiring structure, wiri...
- Publication number 20020074660
- Publication date Jun 20, 2002
- FUJITSU LIMITED
- Shinji Fukasawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and layout data generation apparatus
- Publication number 20020074571
- Publication date Jun 20, 2002
- FUJITSU LIMITED
- Shinji Fukasawa
- G06 - COMPUTING CALCULATING COUNTING

Shinji Fukasawa

Person

Patents Grantslast 30 patents

Method for eliminating hold error in scan chain

Layout method for semiconductor integrated circuit, layout program...

Method and apparatus for laying out cells in a semiconductor device

Semiconductor device and layout data generation apparatus

Patents Applicationslast 30 patents

Method for eliminating hold error in scan chain

Method and apparatus for laying out cells in a semiconductor device

Layout method for semiconductor integrated circuit, layout program...

Semiconductor device having a multiple layer wiring structure, wiri...

Semiconductor device having a multiple layer wiring structure, wiri...

Semiconductor device having a multiple layer wiring structure, wiri...

Semiconductor device and layout data generation apparatus