Shinobu Nakamura

Person

Kanagawa, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,730,366
- Issue date Jun 1, 2010
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,469,367
- Issue date Dec 23, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital PLL device
- Patent number 7,342,986
- Issue date Mar 11, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase error determination method and digital phase-locked loop system
- Patent number 7,315,968
- Issue date Jan 1, 2008
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop circuit for reproducing a channel clock
- Patent number 6,992,958
- Issue date Jan 31, 2006
- Sony Corporation
- Mamoru Kudo
- E05 - LOCKS KEYS WINDOW OR DOOR FITTINGS SAFES
Information Patent Grant
Disc player reproduction circuit with reproduction speed dependent VFO
- Patent number 6,081,492
- Issue date Jun 27, 2000
- Sony Corporation
- Nobuyuki Asai
- G11 - INFORMATION STORAGE
Information Patent Grant
Disc player apparatus having a disc rotational speed controller
- Patent number 5,694,380
- Issue date Dec 2, 1997
- Sony Corporation
- Kazutoshi Shimizume
- G11 - INFORMATION STORAGE
Information Patent Grant
Disc player apparatus having a signal processing circuit which prod...
- Patent number 5,636,192
- Issue date Jun 3, 1997
- Sony Corporation
- Kazutoshi Shimizume
- G11 - INFORMATION STORAGE
Information Patent Grant
Optical disc player with shockproof controller and method of proces...
- Patent number 5,508,983
- Issue date Apr 16, 1996
- Sony Corporation
- Shinobu Nakamura
- G11 - INFORMATION STORAGE
Information Patent Grant
EFM modulator for controlling digital sum variation of encoded data
- Patent number 5,486,827
- Issue date Jan 23, 1996
- Sony Corporation
- Kazutoshi Shimizume
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070094549
- Publication date Apr 26, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20070088992
- Publication date Apr 19, 2007
- Sony Corporation
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Phase error determination method and digital phase-locked loop system
- Publication number 20050022076
- Publication date Jan 27, 2005
- Shinobu Nakamura
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital PLL device
- Publication number 20040264623
- Publication date Dec 30, 2004
- Shinobu Nakamura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase-locked loop circuit
- Publication number 20020105365
- Publication date Aug 8, 2002
- Mamoru Kudo
- E05 - LOCKS KEYS WINDOW OR DOOR FITTINGS SAFES

Shinobu Nakamura

Person

Patents Grantslast 30 patents

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Digital PLL device

Phase error determination method and digital phase-locked loop system

Phase-locked loop circuit for reproducing a channel clock

Disc player reproduction circuit with reproduction speed dependent VFO

Disc player apparatus having a disc rotational speed controller

Disc player apparatus having a signal processing circuit which prod...

Optical disc player with shockproof controller and method of proces...

EFM modulator for controlling digital sum variation of encoded data

Patents Applicationslast 30 patents

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Phase error determination method and digital phase-locked loop system

Digital PLL device

Phase-locked loop circuit