Shishir Kumar

Person

Uttar Pradesh, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing memory device bitline leakage
- Patent number 12,354,656
- Issue date Jul 8, 2025
- Synopsys, Inc.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Interface level-shifter dual-rail memory architecture
- Patent number 12,340,864
- Issue date Jun 24, 2025
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay circuit
- Patent number 12,316,326
- Issue date May 27, 2025
- Synopsys, Inc.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing spurious write operations in a memory device
- Patent number 12,272,424
- Issue date Apr 8, 2025
- Synopsys, Inc.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain compression for testing memory of a system on a chip
- Patent number 12,112,818
- Issue date Oct 8, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply tracking circuitry for embedded memories
- Patent number 12,094,513
- Issue date Sep 17, 2024
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port memory cell with improved access resistance
- Patent number 11,889,675
- Issue date Jan 30, 2024
- STMicroelectronics International N.V.
- Tushar Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing of comparators within a memory safety logic circuit using a...
- Patent number 11,742,045
- Issue date Aug 29, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Rohit Bhasin
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port memory cell with improved access resistance
- Patent number 11,532,633
- Issue date Dec 20, 2022
- STMicroelectronics International N.V.
- Tushar Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for at speed detection of a word line fault cond...
- Patent number 11,521,697
- Issue date Dec 6, 2022
- STMicroelectronics International, N.V.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for at speed detection of a word line fault cond...
- Patent number 11,393,532
- Issue date Jul 19, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Tanmoy Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Robust adaptive method and circuit for controlling a timing window...
- Patent number 11,195,576
- Issue date Dec 7, 2021
- STMicroelectronics International N.V.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port memory cell with improved access resistance
- Patent number 11,152,376
- Issue date Oct 19, 2021
- STMicroelectronics International N.V.
- Tushar Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for detection of single bit upsets in generation of interna...
- Patent number 11,025,252
- Issue date Jun 1, 2021
- STMicroelectronics International N.V.
- Shishir Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testing of comparators within a memory safety logic circuit using a...
- Patent number 10,998,077
- Issue date May 4, 2021
- STMicroelectronics International N.V.
- Rohit Bhasin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for adaptive read-write operation in self-timed...
- Patent number 10,706,915
- Issue date Jul 7, 2020
- STMicroelectronics International N.V.
- Abhishek Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM read multiplexer including replica transistors
- Patent number 10,311,944
- Issue date Jun 4, 2019
- STMicroelectronics International N.V.
- Dhori Kedar Janardan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for adaptive read-write operation in self-timed...
- Patent number 10,283,191
- Issue date May 7, 2019
- STMicroelectronics International N.V.
- Abhishek Pathak
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM read multiplexer including replica transistors
- Patent number 10,037,794
- Issue date Jul 31, 2018
- STMicroelectronics International N.V.
- Dhori Kedar Janardan
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for a pulse generator
- Patent number 9,590,602
- Issue date Mar 7, 2017
- STMicroelectronics International N.V.
- Shishir Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective dual cycle write operation for a self-timed memory
- Patent number 9,324,414
- Issue date Apr 26, 2016
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage dual supply memory cell with two word lines and activat...
- Patent number 9,165,642
- Issue date Oct 20, 2015
- STMicroelectronics International N.V.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay introducing circuit in self timed memory
- Patent number 9,147,453
- Issue date Sep 29, 2015
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port SRAM having reduced cell size and rectangular shape
- Patent number 9,006,841
- Issue date Apr 14, 2015
- STMicroelectronics International N.V.
- Shishir Kumar
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Programmable delay introducing circuit in self-timed memory
- Patent number 8,963,053
- Issue date Feb 24, 2015
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay introducing circuit in self timed memory
- Patent number 8,138,455
- Issue date Mar 20, 2012
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier providing low capacitance with reduced resolution time
- Patent number 7,545,180
- Issue date Jun 9, 2009
- STMicroelectronics Pvt. Ltd.
- Ankur Goel
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Reducing Memory Device Bitline Leakage
- Publication number 20240038300
- Publication date Feb 1, 2024
- Synopsys, Inc.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING SPURIOUS WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20230307019
- Publication date Sep 28, 2023
- Synopsys, Inc.
- Shishir KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE
- Publication number 20230260555
- Publication date Aug 17, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES
- Publication number 20230125268
- Publication date Apr 27, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE
- Publication number 20230091970
- Publication date Mar 23, 2023
- STMicroelectronics International N.V.
- Tushar SHARMA
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP
- Publication number 20230005562
- Publication date Jan 5, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE
- Publication number 20220020754
- Publication date Jan 20, 2022
- STMicroelectronics International N.V.
- Tushar SHARMA
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...
- Publication number 20210225453
- Publication date Jul 22, 2021
- STMicroelectronics International N.V.
- Rohit BHASIN
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...
- Publication number 20200342940
- Publication date Oct 29, 2020
- STMicroelectronics International N.V.
- Tanmoy ROY
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...
- Publication number 20200243153
- Publication date Jul 30, 2020
- STMicroelectronics International, N.V.
- Shishir KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...
- Publication number 20200219579
- Publication date Jul 9, 2020
- STMicroelectronics International N.V.
- Rohit BHASIN
- G11 - INFORMATION STORAGE
Information Patent Application
ROBUST ADAPTIVE METHOD AND CIRCUIT FOR CONTROLLING A TIMING WINDOW...
- Publication number 20200118617
- Publication date Apr 16, 2020
- STMicroelectronics International N.V.
- Shishir KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT FOR DETECTION OF SINGLE BIT UPSETS IN GENERATION OF INTERNA...
- Publication number 20200099378
- Publication date Mar 26, 2020
- STMicroelectronics International N.V.
- Shishir KUMAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED...
- Publication number 20190279707
- Publication date Sep 12, 2019
- STMicroelectronics International N.V.
- Abhishek PATHAK
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE
- Publication number 20190198508
- Publication date Jun 27, 2019
- STMicroelectronics International N.V.
- Tushar SHARMA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM READ MULTIPLEXER INCLUDING REPLICA TRANSISTORS
- Publication number 20190035454
- Publication date Jan 31, 2019
- STMicroelectronics International N.V.
- Dhori Kedar Janardan
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for a Pulse Generator
- Publication number 20150365080
- Publication date Dec 17, 2015
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY
- Publication number 20150055400
- Publication date Feb 26, 2015
- STMicroelectronics International N.V
- NISHU KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY
- Publication number 20150029795
- Publication date Jan 29, 2015
- STMicroelectronics International N.V
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE DUAL SUPPLY MEMORY CELL WITH TWO WORD LINES AND ACTIVAT...
- Publication number 20140204656
- Publication date Jul 24, 2014
- STMicroelectronics International N.V
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT SRAM HAVING REDUCED CELL SIZE AND RECTANGULAR SHAPE
- Publication number 20130170275
- Publication date Jul 4, 2013
- STMicroelectronics Pvt. Ltd.
- Shishir Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF-TIMED MEMORY
- Publication number 20120170393
- Publication date Jul 5, 2012
- STMICROELECTRONICS PVT. LTD.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER PROVIDING LOW CAPACITANCE WITH REDUCED RESOLUTION TIME
- Publication number 20080143390
- Publication date Jun 19, 2008
- STMICROELECTRONICS PVT. LTD.
- Ankur Goel
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY
- Publication number 20070201287
- Publication date Aug 30, 2007
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE

Shishir Kumar

Person

Patents Grantslast 30 patents

Reducing memory device bitline leakage

Interface level-shifter dual-rail memory architecture

Delay circuit

Reducing spurious write operations in a memory device

Scan chain compression for testing memory of a system on a chip

Power supply tracking circuitry for embedded memories

Dual port memory cell with improved access resistance

Testing of comparators within a memory safety logic circuit using a...

Dual port memory cell with improved access resistance

Circuit and method for at speed detection of a word line fault cond...

Circuit and method for at speed detection of a word line fault cond...

Robust adaptive method and circuit for controlling a timing window...

Dual port memory cell with improved access resistance

Circuit for detection of single bit upsets in generation of interna...

Testing of comparators within a memory safety logic circuit using a...

Method and circuit for adaptive read-write operation in self-timed...

SRAM read multiplexer including replica transistors

Method and circuit for adaptive read-write operation in self-timed...

SRAM read multiplexer including replica transistors

System and method for a pulse generator

Selective dual cycle write operation for a self-timed memory

Low voltage dual supply memory cell with two word lines and activat...

Programmable delay introducing circuit in self timed memory

Dual port SRAM having reduced cell size and rectangular shape

Programmable delay introducing circuit in self-timed memory

Programmable delay introducing circuit in self timed memory

Sense amplifier providing low capacitance with reduced resolution time

Patents Applicationslast 30 patents

Reducing Memory Device Bitline Leakage

REDUCING SPURIOUS WRITE OPERATIONS IN A MEMORY DEVICE

INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE

POWER SUPPLY TRACKING CIRCUITRY FOR EMBEDDED MEMORIES

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

SCAN CHAIN COMPRESSION FOR TESTING MEMORY OF A SYSTEM ON A CHIP

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...

CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...

CIRCUIT AND METHOD FOR AT SPEED DETECTION OF A WORD LINE FAULT COND...

TESTING OF COMPARATORS WITHIN A MEMORY SAFETY LOGIC CIRCUIT USING A...

ROBUST ADAPTIVE METHOD AND CIRCUIT FOR CONTROLLING A TIMING WINDOW...

CIRCUIT FOR DETECTION OF SINGLE BIT UPSETS IN GENERATION OF INTERNA...

METHOD AND CIRCUIT FOR ADAPTIVE READ-WRITE OPERATION IN SELF-TIMED...

DUAL PORT MEMORY CELL WITH IMPROVED ACCESS RESISTANCE

SRAM READ MULTIPLEXER INCLUDING REPLICA TRANSISTORS

System and Method for a Pulse Generator

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY

SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY

LOW VOLTAGE DUAL SUPPLY MEMORY CELL WITH TWO WORD LINES AND ACTIVAT...

DUAL PORT SRAM HAVING REDUCED CELL SIZE AND RECTANGULAR SHAPE

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF-TIMED MEMORY

SENSE AMPLIFIER PROVIDING LOW CAPACITANCE WITH REDUCED RESOLUTION TIME

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY