Shiv Kumar Vats

Person

Greater Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Scan circuit and method
- Patent number 11,726,140
- Issue date Aug 15, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for scan testing
- Patent number 11,714,131
- Issue date Aug 1, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit for dynamic checking for faults on functional and BIST...
- Patent number 10,802,077
- Issue date Oct 13, 2020
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
- Publication number 20240426907
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Application
POWER REDUCTION AND EFFECTIVE TIMING EXCEPTIONS HANDLING IN AT-SPEE...
- Publication number 20240427366
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT
- Publication number 20240250668
- Publication date Jul 25, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CIRCUIT AND METHOD
- Publication number 20240012051
- Publication date Jan 11, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CIRCUIT AND METHOD
- Publication number 20220244308
- Publication date Aug 4, 2022
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST CIRCUIT FOR DYNAMIC CHECKING FOR FAULTS ON FUNCTIONAL AND BIST...
- Publication number 20200333399
- Publication date Oct 22, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G01 - MEASURING TESTING

Shiv Kumar Vats

Person

Patents Grantslast 30 patents

Scan circuit and method

Circuit and method for scan testing

Test circuit for dynamic checking for faults on functional and BIST...

Patents Applicationslast 30 patents

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

POWER REDUCTION AND EFFECTIVE TIMING EXCEPTIONS HANDLING IN AT-SPEE...

AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT

SCAN CIRCUIT AND METHOD

SCAN CIRCUIT AND METHOD

TEST CIRCUIT FOR DYNAMIC CHECKING FOR FAULTS ON FUNCTIONAL AND BIST...