Shivnandan Kaushik

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-impact firmware update
- Patent number 11,977,638
- Issue date May 7, 2024
- Ampere Computing LLC
- Sachhidh Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System-on-chip management controller
- Patent number 11,966,750
- Issue date Apr 23, 2024
- Ampere Computing LLC
- Shivnandan Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 10,452,403
- Issue date Oct 22, 2019
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution of a plurality...
- Patent number 9,990,206
- Issue date Jun 5, 2018
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,875,102
- Issue date Jan 23, 2018
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,766,891
- Issue date Sep 19, 2017
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 9,720,697
- Issue date Aug 1, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 9,383,997
- Issue date Jul 5, 2016
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 9,069,605
- Issue date Jun 30, 2015
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for communicating interrupts in a computer system
- Patent number 9,043,521
- Issue date May 26, 2015
- Intel Corporation
- Keshavan Tiruvallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inter-processor interrupts
- Patent number 8,984,199
- Issue date Mar 17, 2015
- Intel Corporation
- Per Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,887,174
- Issue date Nov 11, 2014
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for instruction set based thread execution on a plurality...
- Patent number 8,719,819
- Issue date May 6, 2014
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to schedule threads on OS-sequestered sequencers without...
- Patent number 8,607,235
- Issue date Dec 10, 2013
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transparent support for operating system services for a sequestered...
- Patent number 8,516,483
- Issue date Aug 20, 2013
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 8,479,217
- Issue date Jul 2, 2013
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Primitives to enhance thread-level speculation
- Patent number 8,332,619
- Issue date Dec 11, 2012
- Intel Corporation
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for communicating interrupts in a computer system
- Patent number 8,312,198
- Issue date Nov 13, 2012
- Intel Corporation
- Keshavan Tiruvallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for context state management to reduce save and restore o...
- Patent number 8,171,268
- Issue date May 1, 2012
- Intel Corporation
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor selection for an interrupt based on willingness to accept...
- Patent number 8,032,681
- Issue date Oct 4, 2011
- Intel Corporation
- James B. Crossland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method for persistent user-level thread
- Patent number 8,028,295
- Issue date Sep 27, 2011
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for monitoring instruction set based thread execution on...
- Patent number 8,010,969
- Issue date Aug 30, 2011
- Intel Corporation
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing capacity on demand
- Patent number 7,979,699
- Issue date Jul 12, 2011
- Intel Corporation
- Deep K. Buch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Primitives to enhance thread-level speculation
- Patent number 7,882,339
- Issue date Feb 1, 2011
- Intel Corporation
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for enumeration of processors during hot-plug...
- Patent number 7,822,900
- Issue date Oct 26, 2010
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor selection for an interrupt identifying a processor cluster
- Patent number 7,769,938
- Issue date Aug 3, 2010
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for processor power state aware distribution of lowest pr...
- Patent number 7,761,720
- Issue date Jul 20, 2010
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequencer address management
- Patent number 7,743,233
- Issue date Jun 22, 2010
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hot plug interface control method and apparatus
- Patent number 7,673,090
- Issue date Mar 2, 2010
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queued locks using monitor-memory wait
- Patent number 7,640,384
- Issue date Dec 29, 2009
- Intel Corporation
- Per Hammarlund
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW-IMPACT FIRMWARE UPDATE
- Publication number 20240005003
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Sachhidh KANNAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-ON-CHIP MANAGEMENT CONTROLLER
- Publication number 20240004668
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Shivnandan KAUSHIK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS-RANGE MEMORY MIRRORING IN A COMPUTER SYSTEM, AND RELATED ME...
- Publication number 20230176749
- Publication date Jun 8, 2023
- Ampere Computing LLC
- Sebastien Hily
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20170102944
- Publication date Apr 13, 2017
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20170010895
- Publication date Jan 12, 2017
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20160274910
- Publication date Sep 22, 2016
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20160019067
- Publication date Jan 21, 2016
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM
- Publication number 20140136746
- Publication date May 15, 2014
- Keshavan Tiruvallur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...
- Publication number 20140115594
- Publication date Apr 24, 2014
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20130275735
- Publication date Oct 17, 2013
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY...
- Publication number 20130219399
- Publication date Aug 22, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20130073835
- Publication date Mar 21, 2013
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...
- Publication number 20130054940
- Publication date Feb 28, 2013
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20120084536
- Publication date Apr 5, 2012
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Monitoring Instruction Set Based Thread Execution on...
- Publication number 20120017221
- Publication date Jan 19, 2012
- Richard A. Hankins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, System, And Method For Persistent User-Level Thread
- Publication number 20110314480
- Publication date Dec 22, 2011
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING CAPACITY ON DEMAND
- Publication number 20110246750
- Publication date Oct 6, 2011
- Deep K. BUCH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION
- Publication number 20110087867
- Publication date Apr 14, 2011
- Quinn A. Jacobson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ENUMERATION OF PROCESSORS DURING HOT-PLUG...
- Publication number 20090106471
- Publication date Apr 23, 2009
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATION OF LOGICAL APIC ID WITH CLUSTER ID AND INTRA-CLUSTER ID
- Publication number 20090070551
- Publication date Mar 12, 2009
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER
- Publication number 20090070511
- Publication date Mar 12, 2009
- Intel Corporation
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT...
- Publication number 20090070510
- Publication date Mar 12, 2009
- Intel Corporation
- James B. Crossland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Technique for context state management
- Publication number 20080133898
- Publication date Jun 5, 2008
- Chris J. Newburn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Queued locks using monitor-memory wait
- Publication number 20080022141
- Publication date Jan 24, 2008
- Per Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Queued locks using monitor-memory wait
- Publication number 20070162774
- Publication date Jul 12, 2007
- Intel Corporation
- Per Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for processor power state aware distribution of lowest pr...
- Publication number 20070143514
- Publication date Jun 21, 2007
- Shivnandan D. Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus, system, and method for persistent user-level thread
- Publication number 20070079301
- Publication date Apr 5, 2007
- Intel Corporation
- Gautham Chinya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling optimizations for user-level threads
- Publication number 20070074217
- Publication date Mar 29, 2007
- Ryan Rakvic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OS and firmware coordinated error handling using transparent firmwa...
- Publication number 20070061634
- Publication date Mar 15, 2007
- Suresh Marisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for instruction set based thread execution on a plurality...
- Publication number 20070006231
- Publication date Jan 4, 2007
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING

Shivnandan Kaushik

Person

Patents Grantslast 30 patents

Low-impact firmware update

System-on-chip management controller

Mechanism for instruction set based thread execution on a plurality...

Mechanism for instruction set based thread execution of a plurality...

Apparatus, system, and method for persistent user-level thread

Apparatus, system, and method for persistent user-level thread

Mechanism for instruction set based thread execution on a plurality...

Apparatus, system, and method for persistent user-level thread

Mechanism to schedule threads on OS-sequestered sequencers without...

Technique for communicating interrupts in a computer system

Inter-processor interrupts

Mechanism for monitoring instruction set based thread execution on...

Mechanism for instruction set based thread execution on a plurality...

Mechanism to schedule threads on OS-sequestered sequencers without...

Transparent support for operating system services for a sequestered...

Apparatus, system, and method for persistent user-level thread

Primitives to enhance thread-level speculation

Technique for communicating interrupts in a computer system

Technique for context state management to reduce save and restore o...

Processor selection for an interrupt based on willingness to accept...

Apparatus, system, and method for persistent user-level thread

Mechanism for monitoring instruction set based thread execution on...

Processing capacity on demand

Primitives to enhance thread-level speculation

Apparatus and method for enumeration of processors during hot-plug...

Processor selection for an interrupt identifying a processor cluster

Mechanism for processor power state aware distribution of lowest pr...

Sequencer address management

Hot plug interface control method and apparatus

Queued locks using monitor-memory wait

Patents Applicationslast 30 patents

LOW-IMPACT FIRMWARE UPDATE

SYSTEM-ON-CHIP MANAGEMENT CONTROLLER

ADDRESS-RANGE MEMORY MIRRORING IN A COMPUTER SYSTEM, AND RELATED ME...

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

TECHNIQUE FOR COMMUNICATING INTERRUPTS IN A COMPUTER SYSTEM

MECHANISM TO SCHEDULE THREADS ON OS-SEQUESTERED SEQUENCERS WITHOUT...

Apparatus, System, And Method For Persistent User-Level Thread

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION OF A PLURALITY...

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY...

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

Mechanism for Monitoring Instruction Set Based Thread Execution on...

Apparatus, System, And Method For Persistent User-Level Thread

PROCESSING CAPACITY ON DEMAND

PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION

APPARATUS AND METHOD FOR ENUMERATION OF PROCESSORS DURING HOT-PLUG...

CREATION OF LOGICAL APIC ID WITH CLUSTER ID AND INTRA-CLUSTER ID

PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER

PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT...

Technique for context state management

Queued locks using monitor-memory wait

Queued locks using monitor-memory wait

Mechanism for processor power state aware distribution of lowest pr...

Apparatus, system, and method for persistent user-level thread

Scheduling optimizations for user-level threads

OS and firmware coordinated error handling using transparent firmwa...

Mechanism for instruction set based thread execution on a plurality...