Shoujun Wang

Person

Kanata, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 9,077,330
- Issue date Jul 7, 2015
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 8,570,197
- Issue date Oct 29, 2013
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 8,217,693
- Issue date Jul 10, 2012
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Linear monotonic delay chain circuit
- Patent number 8,115,532
- Issue date Feb 14, 2012
- Integrated Device Technology, Inc.
- Shengyuan Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 7,902,888
- Issue date Mar 8, 2011
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-adjusted pre-emphasis and equalization for data communication
- Patent number 7,848,402
- Issue date Dec 7, 2010
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Serializer circuitry for high-speed serial data transmitters on pro...
- Patent number 7,848,318
- Issue date Dec 7, 2010
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Duty cycle correction methods and circuits
- Patent number 7,839,192
- Issue date Nov 23, 2010
- Altera Corporation
- Shoujun Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced power differential type termination circuit
- Patent number 7,750,666
- Issue date Jul 6, 2010
- Integrated Device Technology, Inc.
- Yu Min Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Built-in at-speed bit error ratio tester
- Patent number 7,743,288
- Issue date Jun 22, 2010
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for equalization in high-speed backplane data...
- Patent number 7,697,603
- Issue date Apr 13, 2010
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for simulating link performance
- Patent number 7,693,691
- Issue date Apr 6, 2010
- Altera Corporation
- Yuming Tao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-loss impedance-matched source-follower for repeating or switchi...
- Patent number 7,679,395
- Issue date Mar 16, 2010
- Integrated Device Technology, Inc.
- Yunfu Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...
- Patent number 7,619,460
- Issue date Nov 17, 2009
- Altera Corporation
- Haitao Mei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual-mode LVDS/CML transmitter methods and apparatus
- Patent number 7,598,779
- Issue date Oct 6, 2009
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock data recovery loop with separate proportional path
- Patent number 7,580,497
- Issue date Aug 25, 2009
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multitap fractional baud period pre-emphasis for data transmission
- Patent number 7,528,635
- Issue date May 5, 2009
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of clock signal with data signal
- Patent number 7,486,752
- Issue date Feb 3, 2009
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic frequency divider with improved leakage tolerance
- Patent number 7,453,294
- Issue date Nov 18, 2008
- Altera Corporation
- Shoujun Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage controlled oscillator circuitry and methods
- Patent number 7,414,484
- Issue date Aug 19, 2008
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for wide tuning-range ring oscillators
- Patent number 7,388,443
- Issue date Jun 17, 2008
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Charge pump with reduced current mismatch
- Patent number 7,385,429
- Issue date Jun 10, 2008
- Altera Corporation
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...
- Patent number 7,352,229
- Issue date Apr 1, 2008
- Altera Corporation
- Haitao Mei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock circuitry for programmable logic devices
- Patent number 7,304,498
- Issue date Dec 4, 2007
- Altera Corporation
- William W Bereza
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive communication methods and apparatus
- Patent number 7,239,849
- Issue date Jul 3, 2007
- Altera Corporation
- Bill Bereza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential signal detector methods and apparatus
- Patent number 7,224,191
- Issue date May 29, 2007
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multitap fractional baud period pre-emphasis for data transmission
- Patent number 7,196,557
- Issue date Mar 27, 2007
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential signal detector methods and apparatus
- Patent number 7,157,944
- Issue date Jan 2, 2007
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Alignment of recovered clock with data signal
- Patent number 7,143,312
- Issue date Nov 28, 2006
- Altera Corporation
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and methods for wide tuning-range ring oscillators
- Patent number 7,061,334
- Issue date Jun 13, 2006
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20140009188
- Publication date Jan 9, 2014
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CHARGE PUMP WITH REDUCED CURRENT MISMATCH
- Publication number 20110156806
- Publication date Jun 30, 2011
- Haitao Mei
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...
- Publication number 20110068845
- Publication date Mar 24, 2011
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Reduced Power Differential Type Termination Circuit
- Publication number 20100066404
- Publication date Mar 18, 2010
- Yu Min Zhang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW-LOSS IMPEDANCE-MATCHED SOURCE-FOLLOWER FOR REPEATING OR SWITCHI...
- Publication number 20100066410
- Publication date Mar 18, 2010
- Yunfu Yang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS FOR TIME-DOMAIN PRE-EMPHASIS AND TIME-DOMAIN EQUALIZATION...
- Publication number 20100027607
- Publication date Feb 4, 2010
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Linear monotonic delay chain circuit
- Publication number 20100007398
- Publication date Jan 14, 2010
- Integrated Device Technology, Inc.
- Shengyuan Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...
- Publication number 20080197906
- Publication date Aug 21, 2008
- Altera Corporation
- Haitao Mei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multitap fractional baud period pre-emphasis for data transmission
- Publication number 20070241795
- Publication date Oct 18, 2007
- Altera Corporation
- Tad Kwasniewski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Voltage controlled oscillator circuitry and methods
- Publication number 20070069831
- Publication date Mar 29, 2007
- Altera Corporation
- Tad Kwasniewski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Serializer circuitry for high-speed serial data transmitters on pro...
- Publication number 20070030184
- Publication date Feb 8, 2007
- Altera Corporation
- Toan Thanh Nguyen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Clock circuitry for programmable logic devices
- Publication number 20070019766
- Publication date Jan 25, 2007
- Altera Corporation
- William W. Bereza
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock data recovery loop with separate proportional path
- Publication number 20070002993
- Publication date Jan 4, 2007
- ALTERA CORPORATION, a corporation of Delaware
- Shoujun Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and methods for wide tuning-range ring oscillators
- Publication number 20060192623
- Publication date Aug 31, 2006
- Altera Corporation
- Mashkoor Baig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input stage threshold adjustment for high speed data communications
- Publication number 20050160327
- Publication date Jul 21, 2005
- Altera Corporation
- Mashkoor Baig
- G01 - MEASURING TESTING
Information Patent Application
Pre-emphasis circuitry and methods
- Publication number 20050093580
- Publication date May 5, 2005
- Altera Corporation
- Mashkoor Baig
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Adaptive communication methods and apparatus
- Publication number 20050095988
- Publication date May 5, 2005
- Altera Corporation
- Bill Bereza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Active peaking using differential pairs of transistors
- Publication number 20030141919
- Publication date Jul 31, 2003
- Shoujun Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Shoujun Wang

Person

Patents Grantslast 30 patents

Serializer circuitry for high-speed serial data transmitters on pro...

Serializer circuitry for high-speed serial data transmitters on pro...

Charge pump with reduced current mismatch

Linear monotonic delay chain circuit

Charge pump with reduced current mismatch

Phase-adjusted pre-emphasis and equalization for data communication

Serializer circuitry for high-speed serial data transmitters on pro...

Duty cycle correction methods and circuits

Reduced power differential type termination circuit

Built-in at-speed bit error ratio tester

Methods and apparatus for equalization in high-speed backplane data...

Systems and methods for simulating link performance

Low-loss impedance-matched source-follower for repeating or switchi...

Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...

Dual-mode LVDS/CML transmitter methods and apparatus

Clock data recovery loop with separate proportional path

Multitap fractional baud period pre-emphasis for data transmission

Alignment of clock signal with data signal

Dynamic frequency divider with improved leakage tolerance

Voltage controlled oscillator circuitry and methods

Apparatus and method for wide tuning-range ring oscillators

Charge pump with reduced current mismatch

Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...

Clock circuitry for programmable logic devices

Adaptive communication methods and apparatus

Differential signal detector methods and apparatus

Multitap fractional baud period pre-emphasis for data transmission

Differential signal detector methods and apparatus

Alignment of recovered clock with data signal

Apparatus and methods for wide tuning-range ring oscillators

Patents Applicationslast 30 patents

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

CHARGE PUMP WITH REDUCED CURRENT MISMATCH

SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PRO...

Reduced Power Differential Type Termination Circuit

LOW-LOSS IMPEDANCE-MATCHED SOURCE-FOLLOWER FOR REPEATING OR SWITCHI...

APPARATUS FOR TIME-DOMAIN PRE-EMPHASIS AND TIME-DOMAIN EQUALIZATION...

Linear monotonic delay chain circuit

Reference clock receiver compliant with LVPECL, LVDS and PCI-Expres...

Multitap fractional baud period pre-emphasis for data transmission

Voltage controlled oscillator circuitry and methods

Serializer circuitry for high-speed serial data transmitters on pro...

Clock circuitry for programmable logic devices

Clock data recovery loop with separate proportional path

Apparatus and methods for wide tuning-range ring oscillators

Input stage threshold adjustment for high speed data communications

Pre-emphasis circuitry and methods

Adaptive communication methods and apparatus

Active peaking using differential pairs of transistors