Shree Kant

Person

Union City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive timing control circuitry to address leakage
- Patent number 8,482,316
- Issue date Jul 9, 2013
- Oracle International Corporation
- Zhen Wu Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for performing swap operation and apparatus for implementing...
- Patent number 7,484,061
- Issue date Jan 27, 2009
- Sun Microsystems, Inc.
- Zhen Wu Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and pipeline architecture for processing multiple swap reque...
- Patent number 7,337,305
- Issue date Feb 26, 2008
- Sun Microsystems, Inc.
- Kenway W. Tam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of a read scheme for multi-threaded regist...
- Patent number 7,203,100
- Issue date Apr 10, 2007
- Sun Mircosystems, Inc.
- Shree Kant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient method of data transfer between register files and memories
- Patent number 7,136,308
- Issue date Nov 14, 2006
- Sun Microsystems, Inc.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and circuits for balancing bitline precharge
- Patent number 6,940,771
- Issue date Sep 6, 2005
- Sun Microsystems, Inc.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed single ended sense amplifier with built-in multiplexer
- Patent number 6,900,668
- Issue date May 31, 2005
- Sun Microsystems Inc
- Kenway W. Tam
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power memory design with asymmetric bit line driver
- Patent number 6,707,721
- Issue date Mar 16, 2004
- Sun Microsystems, Inc.
- Gajendra Singh
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance address decode technique for arrays
- Patent number 6,646,951
- Issue date Nov 11, 2003
- Sun Microsystems, Inc.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power read scheme for memory array structures
- Patent number 6,442,099
- Issue date Aug 27, 2002
- Sun Microsystems, Inc.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding of a register file
- Patent number 6,320,813
- Issue date Nov 20, 2001
- Sun Microsystems, Inc.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for sizing PMOS pull-up devices
- Patent number 6,316,301
- Issue date Nov 13, 2001
- Sun Microsystems, Inc.
- Shree Kant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single ended read scheme with segmented bitline of multi-port regis...
- Patent number 6,038,193
- Issue date Mar 14, 2000
- Sun Microsystems, Inc.
- Yong Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Single ended read scheme with global bitline of multi-port register...
- Patent number 6,014,338
- Issue date Jan 11, 2000
- Sun Microsystems, Inc.
- Yong Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Efficient method of data transfer between register files and memories
- Publication number 20060092710
- Publication date May 4, 2006
- SUN MICROSYSTEMS, INC.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Application
Efficient implementation of a read scheme for multi-threaded regist...
- Publication number 20060092711
- Publication date May 4, 2006
- SUN MICROSYSTEMS, INC.
- Shree Kant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED SINGLE ENDED SENSE AMPLIFIER WITH BUILT-IN MULTIPLEXER
- Publication number 20050110527
- Publication date May 26, 2005
- SUN MICROSYSTEMS, INC.
- Kenway W. Tam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Internal pipeline architecture for save/restore operation to reduce...
- Publication number 20050114634
- Publication date May 26, 2005
- SUN MICROSYSTEMS, INC.
- Kenway W. Tam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and circuits for balancing bitline precharge
- Publication number 20040151044
- Publication date Aug 5, 2004
- SUN MICROSYSTEMS, INC.
- Shree Kant
- G11 - INFORMATION STORAGE
Information Patent Application
Low power memory design with asymmetric bit line driver
- Publication number 20030174535
- Publication date Sep 18, 2003
- Gajendra Singh
- G11 - INFORMATION STORAGE
Information Patent Application
High performance address decode technique for arrays
- Publication number 20030076732
- Publication date Apr 24, 2003
- Shree Kant
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Adaptive timing control circuitry to address leakage

Method for performing swap operation and apparatus for implementing...

Method and pipeline architecture for processing multiple swap reque...

Efficient implementation of a read scheme for multi-threaded regist...

Efficient method of data transfer between register files and memories

Methods and circuits for balancing bitline precharge

High speed single ended sense amplifier with built-in multiplexer

Low power memory design with asymmetric bit line driver

High performance address decode technique for arrays

Low power read scheme for memory array structures

Decoding of a register file

Method for sizing PMOS pull-up devices

Single ended read scheme with segmented bitline of multi-port regis...

Single ended read scheme with global bitline of multi-port register...

Patents Applicationslast 30 patents

Efficient method of data transfer between register files and memories

Efficient implementation of a read scheme for multi-threaded regist...

HIGH SPEED SINGLE ENDED SENSE AMPLIFIER WITH BUILT-IN MULTIPLEXER

Internal pipeline architecture for save/restore operation to reduce...

Methods and circuits for balancing bitline precharge

Low power memory design with asymmetric bit line driver

High performance address decode technique for arrays