Shu-Ya Chuang

Person

Hsin-Chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Phase-locked loop with loop gain calibration, gain measurement meth...
- Patent number 8,860,478
- Issue date Oct 14, 2014
- National Chiao Tung University
- Wei-Zen Chen
- G01 - MEASURING TESTING
Information Patent Grant
Fabrication of self-aligned bipolar transistor
- Patent number 6,884,689
- Issue date Apr 26, 2005
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for forming self-aligned bipolar junction tran...
- Patent number 6,774,002
- Issue date Aug 10, 2004
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming shallow trench isolation structure
- Patent number 6,548,373
- Issue date Apr 15, 2003
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of monitoring loss of silicon nitride
- Patent number 6,479,307
- Issue date Nov 12, 2002
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating dynamic random access memories
- Patent number 6,417,036
- Issue date Jul 9, 2002
- United Microelectronics Corp.
- Shu-Ya Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming a shallow trench isolation structure
- Patent number 6,344,415
- Issue date Feb 5, 2002
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Batch scanning method of an image scanner
- Patent number 6,236,770
- Issue date May 22, 2001
- Mustek System Inc.
- Chien-Shu Hsieh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Fabrication method for a compact DRAM cell
- Patent number 6,218,241
- Issue date Apr 17, 2001
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing dynamic random access memory
- Patent number 6,200,854
- Issue date Mar 13, 2001
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully self-aligned method for fabricating transistor and memory
- Patent number 6,190,958
- Issue date Feb 20, 2001
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating dynamic random access memories
- Patent number 6,172,388
- Issue date Jan 9, 2001
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned DRAM cell
- Patent number 6,159,808
- Issue date Dec 12, 2000
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating capacitor
- Patent number 6,159,789
- Issue date Dec 12, 2000
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a shallow trench isolation structure
- Patent number 6,107,159
- Issue date Aug 22, 2000
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a capacitor in a dynamic random access memory
- Patent number 6,083,804
- Issue date Jul 4, 2000
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating dual cylindrical capacitor
- Patent number 5,998,259
- Issue date Dec 7, 1999
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating stack capacitor
- Patent number 5,981,337
- Issue date Nov 9, 1999
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a dynamic random access memory with a vertic...
- Patent number 5,960,282
- Issue date Sep 28, 1999
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating shallow trench isolation structure
- Patent number 5,937,309
- Issue date Aug 10, 1999
- United Semiconductor Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PHASE-LOCKED LOOP WITH LOOP GAIN CALIBRATION, GAIN MEASUREMENT METH...
- Publication number 20140077849
- Publication date Mar 20, 2014
- National Chiao Tung University
- Wei-Zen Chen
- G01 - MEASURING TESTING
Information Patent Application
Fabrication of self-aligned bipolar transistor
- Publication number 20050040470
- Publication date Feb 24, 2005
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method for forming self-aligned bipolar junction tran...
- Publication number 20040082135
- Publication date Apr 29, 2004
- UNITED MICROELECTRONICS CORP.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabrication of self-aligned bipolar transistor
- Publication number 20030096486
- Publication date May 22, 2003
- United Microelectronics Corp.
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a contact pad
- Publication number 20020132191
- Publication date Sep 19, 2002
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MONITORING LOSS OF SILICON NITRIDE
- Publication number 20020127746
- Publication date Sep 12, 2002
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming shallow trench isolation structure
- Publication number 20010029083
- Publication date Oct 11, 2001
- Shu-Ya Chuang
- H01 - BASIC ELECTRIC ELEMENTS

Shu-Ya Chuang

Person

Patents Grantslast 30 patents

Phase-locked loop with loop gain calibration, gain measurement meth...

Fabrication of self-aligned bipolar transistor

Structure and method for forming self-aligned bipolar junction tran...

Method for forming shallow trench isolation structure

Method of monitoring loss of silicon nitride

Method of fabricating dynamic random access memories

Method for forming a shallow trench isolation structure

Batch scanning method of an image scanner

Fabrication method for a compact DRAM cell

Method of manufacturing dynamic random access memory

Fully self-aligned method for fabricating transistor and memory

Method of fabricating dynamic random access memories

Method of forming self-aligned DRAM cell

Method for fabricating capacitor

Method for fabricating a shallow trench isolation structure

Method for fabricating a capacitor in a dynamic random access memory

Method of fabricating dual cylindrical capacitor

Method of fabricating stack capacitor

Method for fabricating a dynamic random access memory with a vertic...

Method for fabricating shallow trench isolation structure

Patents Applicationslast 30 patents

PHASE-LOCKED LOOP WITH LOOP GAIN CALIBRATION, GAIN MEASUREMENT METH...

Fabrication of self-aligned bipolar transistor

Structure and method for forming self-aligned bipolar junction tran...

Fabrication of self-aligned bipolar transistor

Method for forming a contact pad

METHOD OF MONITORING LOSS OF SILICON NITRIDE

Method for forming shallow trench isolation structure