Shu Yi Ying

Person

Taichung, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method and layout of an integrated circuit
- Patent number 11,714,947
- Issue date Aug 1, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for latch-up prevention
- Patent number 11,615,227
- Issue date Mar 28, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 11,341,308
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 10,936,780
- Issue date Mar 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for latch-up prevention
- Patent number 10,872,190
- Issue date Dec 22, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 10,402,529
- Issue date Sep 3, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with fill cells
- Patent number 10,331,838
- Issue date Jun 25, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jung-Chan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization for circuit migration
- Patent number 9,672,315
- Issue date Jun 6, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization for circuit migration
- Patent number 9,275,186
- Issue date Mar 1, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock circuit and method for pulsed latch circuits
- Patent number 8,232,824
- Issue date Jul 31, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Hsing Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method for clock skew compensation in voltage scaling
- Patent number 7,746,142
- Issue date Jun 29, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei-Pin Changchein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test site and a method of monitoring via etch depths for semiconduc...
- Patent number 5,900,644
- Issue date May 4, 1999
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Shu-Lan Ying
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test site and a method of monitoring via etch depths for semiconduc...
- Patent number 5,702,956
- Issue date Dec 30, 1997
- Taiwan Semiconductor Manufactoring, Company Ltd
- Shu-Lan Ying
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and resulting device for field inversion free multiple layer...
- Patent number 5,461,254
- Issue date Oct 24, 1995
- Taiwan Semiconductor Manufacturing Company LTD.
- Lih-Shyng Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for field inversion free multiple layer metallurgy VLSI proc...
- Patent number 5,252,515
- Issue date Oct 12, 1993
- Taiwan Semiconductor Manufacturing Company
- Lih-Shyng Tsai
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR LATCH-UP PREVENTION
- Publication number 20240386180
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20220284165
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...
- Publication number 20210374317
- Publication date Dec 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ritesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20210173996
- Publication date Jun 10, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAP CELLS
- Publication number 20200019666
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G01 - MEASURING TESTING
Information Patent Application
METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...
- Publication number 20200004915
- Publication date Jan 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ritesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20190392108
- Publication date Dec 26, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH FILL CELLS
- Publication number 20180165399
- Publication date Jun 14, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jung-Chan YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20180144082
- Publication date May 24, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Optimization for Circuit Migration
- Publication number 20140245251
- Publication date Aug 28, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design Optimization for Circuit Migration
- Publication number 20110035717
- Publication date Feb 10, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Circuit and Method for Pulsed Latch Circuits
- Publication number 20100259308
- Publication date Oct 14, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chung-Hsing Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit and Method for Clock Skew Compensation in Voltage Scaling
- Publication number 20100090738
- Publication date Apr 15, 2010
- Wei-Pin Changchein
- G06 - COMPUTING CALCULATING COUNTING

Shu Yi Ying

Person

Patents Grantslast 30 patents

Method and layout of an integrated circuit

Method and system for latch-up prevention

Method and layout of an integrated circuit

Method and layout of an integrated circuit

Method and system for latch-up prevention

Method and layout of an integrated circuit

Semiconductor device with fill cells

Optimization for circuit migration

Optimization for circuit migration

Clock circuit and method for pulsed latch circuits

Circuit and method for clock skew compensation in voltage scaling

Test site and a method of monitoring via etch depths for semiconduc...

Test site and a method of monitoring via etch depths for semiconduc...

Method and resulting device for field inversion free multiple layer...

Method for field inversion free multiple layer metallurgy VLSI proc...

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR LATCH-UP PREVENTION

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

TAP CELLS

METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING DUMMY PATTERN CONVERS...

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

SEMICONDUCTOR DEVICE WITH FILL CELLS

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

Design Optimization for Circuit Migration

Design Optimization for Circuit Migration

Clock Circuit and Method for Pulsed Latch Circuits

Circuit and Method for Clock Skew Compensation in Voltage Scaling