Shuai MU

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Supporting 8-bit floating point format operands in a computing arch...
- Patent number 12,242,846
- Issue date Mar 4, 2025
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple register allocation sizes for threads
- Patent number 12,210,905
- Issue date Jan 28, 2025
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tanh and sigmoid function execution
- Patent number 12,164,884
- Issue date Dec 10, 2024
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Native support for execution of get exponent, get mantisssa, and sc...
- Patent number 12,067,394
- Issue date Aug 20, 2024
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Native support for execution of get exponent, get mantissa, and sca...
- Patent number 11,625,244
- Issue date Apr 11, 2023
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...
- Publication number 20250085969
- Publication date Mar 13, 2025
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
- Publication number 20250036361
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...
- Publication number 20240403044
- Publication date Dec 5, 2024
- Intel Corporation
- Shuai MU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20240256274
- Publication date Aug 1, 2024
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...
- Publication number 20240103810
- Publication date Mar 28, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...
- Publication number 20230315447
- Publication date Oct 5, 2023
- Intel Corporation
- Shuai MU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS
- Publication number 20220413916
- Publication date Dec 29, 2022
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...
- Publication number 20220405096
- Publication date Dec 22, 2022
- Intel Corporation
- Shuai MU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20220318013
- Publication date Oct 6, 2022
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE CONSTANT CACHE AND CONSTANT ACCESS MECHANISMS
- Publication number 20220308877
- Publication date Sep 29, 2022
- Intel Corporation
- Subramaniam MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TANH AND SIGMOID FUNCTION EXECUTION
- Publication number 20220066737
- Publication date Mar 3, 2022
- Intel Corporation
- Shuai MU
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Supporting 8-bit floating point format operands in a computing arch...

Multiple register allocation sizes for threads

Tanh and sigmoid function execution

Native support for execution of get exponent, get mantisssa, and sc...

Native support for execution of get exponent, get mantissa, and sca...

Patents Applicationslast 30 patents

UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...

FLOATING-POINT CONVERSION VIA AN INTEGER UNIT

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...

NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...

MULTIPLE REGISTER ALLOCATION SIZES FOR THREADS

NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SC...

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

HIGH PERFORMANCE CONSTANT CACHE AND CONSTANT ACCESS MECHANISMS

TANH AND SIGMOID FUNCTION EXECUTION