Shubham Jain

Person

West Lafayette, IN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low precision deep neural network enabled by compensation instructions
- Patent number 12,056,594
- Issue date Aug 6, 2024
- International Business Machines Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special-purpose digital-compute hardware for efficient element-wise...
- Patent number 12,045,612
- Issue date Jul 23, 2024
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ternary in-memory accelerator
- Patent number 11,966,714
- Issue date Apr 23, 2024
- Purdue Research Foundation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable multicast protocol for ring-topology based artificial...
- Patent number 11,831,467
- Issue date Nov 28, 2023
- International Business Machines Corporation
- Shubham Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Ternary in-memory accelerator
- Patent number 11,281,429
- Issue date Mar 22, 2022
- Purdue Research Foundation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bi-scaled deep neural networks
- Patent number 11,263,518
- Issue date Mar 1, 2022
- International Business Machines Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for in-memory computing
- Patent number 10,073,733
- Issue date Sep 11, 2018
- Purdue Research Foundation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DIGITAL COMPUTE HARDWARE FOR EFFICIENT ELEMENT-WISE AND CROSS-VECTO...
- Publication number 20240403045
- Publication date Dec 5, 2024
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE-PARALLEL-DATAFLOW ARTIFICIAL INTELLIGENCE SYSTEM FOR ACCEL...
- Publication number 20240220572
- Publication date Jul 4, 2024
- International Business Machines Corporation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE FOR PARALLEL LAYER-NORM COMPUTE
- Publication number 20240211532
- Publication date Jun 27, 2024
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL-PURPOSE DIGITAL-COMPUTE HARDWARE FOR EFFICIENT ELEMENT-WISE...
- Publication number 20240086192
- Publication date Mar 14, 2024
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STICKIFICATION USING ANYWHERE PADDING TO ACCELERATE DATA MANIPULATION
- Publication number 20240028899
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Swagath VENKATARAMANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE MULTICAST PROTOCOL FOR RING-TOPOLOGY BASED ARTIFICIAL...
- Publication number 20230370304
- Publication date Nov 16, 2023
- International Business Machines Corporation
- Shubham JAIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TWO-DIMENSIONAL MESH FOR COMPUTE-IN-MEMORY ACCELERATOR ARCHITECTURE
- Publication number 20230316060
- Publication date Oct 5, 2023
- International Business Machines Corporation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Data Layout and Alignment for Wide-Vector Accelerator Sys...
- Publication number 20230305841
- Publication date Sep 28, 2023
- International Business Machines Corporation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ORGANIZING SEQUENCES FOR TRANSFORMER COMPUTE
- Publication number 20230169305
- Publication date Jun 1, 2023
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING
- Publication number 20230100564
- Publication date Mar 30, 2023
- International Business Machines Corporation
- Geoffrey Burr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING CONVOLUTION NEURAL NETWORK ON ANALOG RESISTIVE PROCESSING...
- Publication number 20230099608
- Publication date Mar 30, 2023
- International Business Machines Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TERNARY IN-MEMORY ACCELERATOR
- Publication number 20220206751
- Publication date Jun 30, 2022
- Purdue Research Foundation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BI-SCALED DEEP NEURAL NETWORKS
- Publication number 20210103799
- Publication date Apr 8, 2021
- International Business Machines Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TERNARY IN-MEMORY ACCELERATOR
- Publication number 20210089272
- Publication date Mar 25, 2021
- Purdue Research Foundation
- Shubham Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW PRECISION DEEP NEURAL NETWORK ENABLED BY COMPENSATION INSTRUCTIONS
- Publication number 20200005125
- Publication date Jan 2, 2020
- International Business Machines Corporation
- Swagath Venkataramani
- G06 - COMPUTING CALCULATING COUNTING

Shubham Jain

Person

Patents Grantslast 30 patents

Low precision deep neural network enabled by compensation instructions

Special-purpose digital-compute hardware for efficient element-wise...

Ternary in-memory accelerator

Programmable multicast protocol for ring-topology based artificial...

Ternary in-memory accelerator

Bi-scaled deep neural networks

System and method for in-memory computing

Patents Applicationslast 30 patents

DIGITAL COMPUTE HARDWARE FOR EFFICIENT ELEMENT-WISE AND CROSS-VECTO...

PIPELINE-PARALLEL-DATAFLOW ARTIFICIAL INTELLIGENCE SYSTEM FOR ACCEL...

HARDWARE FOR PARALLEL LAYER-NORM COMPUTE

SPECIAL-PURPOSE DIGITAL-COMPUTE HARDWARE FOR EFFICIENT ELEMENT-WISE...

STICKIFICATION USING ANYWHERE PADDING TO ACCELERATE DATA MANIPULATION

PROGRAMMABLE MULTICAST PROTOCOL FOR RING-TOPOLOGY BASED ARTIFICIAL...

TWO-DIMENSIONAL MESH FOR COMPUTE-IN-MEMORY ACCELERATOR ARCHITECTURE

Efficient Data Layout and Alignment for Wide-Vector Accelerator Sys...

ORGANIZING SEQUENCES FOR TRANSFORMER COMPUTE

IMPLICIT VECTOR CONCATENATION WITHIN 2D MESH ROUTING

TRAINING CONVOLUTION NEURAL NETWORK ON ANALOG RESISTIVE PROCESSING...

TERNARY IN-MEMORY ACCELERATOR

BI-SCALED DEEP NEURAL NETWORKS

TERNARY IN-MEMORY ACCELERATOR

LOW PRECISION DEEP NEURAL NETWORK ENABLED BY COMPENSATION INSTRUCTIONS