Shubhendu Sekhar Mukherjee

Person

Southborough, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Managing power in an integrated circuit for high-speed activation
- Patent number 12,145,518
- Issue date Nov 19, 2024
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Pipelines for secure multithread execution
- Patent number 11,886,882
- Issue date Jan 30, 2024
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,868,262
- Issue date Jan 9, 2024
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing out-of-order retirement of instructions based on received...
- Patent number 11,842,198
- Issue date Dec 12, 2023
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prime and probe attack mitigation
- Patent number 11,822,652
- Issue date Nov 21, 2023
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing power in an integrated circuit for high-speed activation
- Patent number 11,766,975
- Issue date Sep 26, 2023
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- B60 - VEHICLES IN GENERAL
Information Patent Grant
System and method for implementing strong load ordering in a proces...
- Patent number 11,748,109
- Issue date Sep 5, 2023
- Marvell Asia Pte, Ltd.
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,615,027
- Issue date Mar 28, 2023
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noisy instructions for side-channel attack mitigation
- Patent number 11,604,873
- Issue date Mar 14, 2023
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for implementing strong load ordering in a proces...
- Patent number 11,550,590
- Issue date Jan 10, 2023
- Marvell Asia Pte, Ltd.
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared mid-level data cache
- Patent number 11,513,958
- Issue date Nov 29, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing load and store instructions for memory barrier handling
- Patent number 11,507,379
- Issue date Nov 22, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector prefetching for computing systems
- Patent number 11,500,779
- Issue date Nov 15, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prime and probe attack mitigation
- Patent number 11,487,874
- Issue date Nov 1, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External way allocation circuitry for processor cores
- Patent number 11,379,368
- Issue date Jul 5, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing prefetch lookahead distance based on memory access latency
- Patent number 11,379,372
- Issue date Jul 5, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential cache block sizing for computing systems
- Patent number 11,379,379
- Issue date Jul 5, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelines for secure multithread execution
- Patent number 11,372,647
- Issue date Jun 28, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing low-level instructions and core interactions in multi-core...
- Patent number 11,327,759
- Issue date May 10, 2022
- Marvell Asia Pte, Ltd.
- David Albert Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning in a processor cache
- Patent number 11,327,890
- Issue date May 10, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic designation of instructions as sensitive for constraining m...
- Patent number 11,307,857
- Issue date Apr 19, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for implementing strong load ordering in a proces...
- Patent number 11,269,644
- Issue date Mar 8, 2022
- Marvell Asia Pte, Ltd.
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microarchitectural sensitive tag flow
- Patent number 11,263,015
- Issue date Mar 1, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing processor core synchronization using interrupts
- Patent number 11,263,043
- Issue date Mar 1, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing out-of-order retirement of instructions
- Patent number 11,194,584
- Issue date Dec 7, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for distributing memory requests
- Patent number 11,188,466
- Issue date Nov 30, 2021
- Marvell Asia Pte, Ltd.
- Richard E. Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing potential faults for speculative page table access
- Patent number 11,176,055
- Issue date Nov 16, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
History table management for a correlated prefetcher
- Patent number 11,126,556
- Issue date Sep 21, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared mid-level data cache
- Patent number 11,093,405
- Issue date Aug 17, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu S. Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mid-level instruction cache
- Patent number 11,036,643
- Issue date Jun 15, 2021
- Marvell Asia Pte, Ltd.
- David H. Asher
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PAGE TABLE ENTRY CACHES WITH MULTIPLE TAG LENGTHS
- Publication number 20240338320
- Publication date Oct 10, 2024
- SiFive, Inc.
- Perrine Peresse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Management In System On A Chip With Securely Partitioned Memo...
- Publication number 20240303205
- Publication date Sep 12, 2024
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Power in an Integrated Circuit for High-Speed Activation
- Publication number 20230391281
- Publication date Dec 7, 2023
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- B60 - VEHICLES IN GENERAL
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20230185720
- Publication date Jun 15, 2023
- Marvell Asia Pte, Ltd.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Implementing Strong Load Ordering in a Proces...
- Publication number 20230099730
- Publication date Mar 30, 2023
- Marvell Asia Pte Ltd.
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor Power Management Using Instruction Throttling
- Publication number 20230019271
- Publication date Jan 19, 2023
- SiFive, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelines for Secure Multithread Execution
- Publication number 20220229667
- Publication date Jul 21, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Designation of Instructions as Sensitive for Constraining I...
- Publication number 20220156076
- Publication date May 19, 2022
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Implementing Strong Load Ordering in a Proces...
- Publication number 20220156080
- Publication date May 19, 2022
- Marvell Asia Pte, Ltd.
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20220114101
- Publication date Apr 14, 2022
- Marvell Asia Pte, Ltd.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Designation of Instructions as Sensitive
- Publication number 20210173651
- Publication date Jun 10, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelines for Secure Multithread Execution
- Publication number 20210173657
- Publication date Jun 10, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Power in an Integrated Circuit for High-Speed Activation
- Publication number 20210016728
- Publication date Jan 21, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- B60 - VEHICLES IN GENERAL
Information Patent Application
Managing Commit Order for an External Instruction Relative to Queue...
- Publication number 20210011729
- Publication date Jan 14, 2021
- Marvell Asia Pte, Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Load and Store Instructions for Memory Barrier Handling
- Publication number 20200379772
- Publication date Dec 3, 2020
- Marvell World Trade Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Trace Information Storage Using Pipeline Instruction Inser...
- Publication number 20200210195
- Publication date Jul 2, 2020
- Marvell International Ltd.
- Gerald Lampert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS
- Publication number 20200183844
- Publication date Jun 11, 2020
- Marvell Semiconductor, Inc.
- Richard E. KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Managing Translation Lookaside Buffer Entries Based on Associativit...
- Publication number 20200174945
- Publication date Jun 4, 2020
- Marvell International Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHING DATA TO REDUCE CACHE MISSES
- Publication number 20200167285
- Publication date May 28, 2020
- Cavium LLC
- David CARLSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING PIPELINE INSTRUCTION INSERTION FOR RECEIVED EXTERNAL INSTR...
- Publication number 20200133680
- Publication date Apr 30, 2020
- Marvell International Ltd.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...
- Publication number 20200097292
- Publication date Mar 26, 2020
- Marvell International Ltd.
- David Albert Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Preventing Information Leakage In Out-Of-Order Machines Due To Miss...
- Publication number 20200034152
- Publication date Jan 30, 2020
- David A. Carlson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING OBSCURED BRANCH PREDICTION INFORMATION
- Publication number 20190227802
- Publication date Jul 25, 2019
- Cavium, Inc.
- Richard Eugene KESSLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING BRANCH PREDICTION INFORMATION FOR DIFFERENT CONTEXTS
- Publication number 20190227803
- Publication date Jul 25, 2019
- Cavium, Inc.
- Shubhendu Sekhar MUKHERJEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING PREDICTOR SELECTION FOR BRANCH PREDICTION
- Publication number 20190227804
- Publication date Jul 25, 2019
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS
- Publication number 20190138232
- Publication date May 9, 2019
- Cavium, LLC
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING CACHE PARTITIONS BASED ON CACHE USAGE INFORMATION
- Publication number 20180373635
- Publication date Dec 27, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING MEMORY ACCESS REQUESTS WITH PREFETCH FOR STREAMS
- Publication number 20180300247
- Publication date Oct 18, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION
- Publication number 20180293100
- Publication date Oct 11, 2018
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING LOCK AND UNLOCK OPERATIONS USING OPERATION PREDICTION
- Publication number 20180293070
- Publication date Oct 11, 2018
- Cavium, Inc.
- Shubhendu Sekhar Mukherjee
- G06 - COMPUTING CALCULATING COUNTING

Shubhendu Sekhar Mukherjee

Person

Patents Grantslast 30 patents

Managing power in an integrated circuit for high-speed activation

Pipelines for secure multithread execution

Methods and systems for distributing memory requests

Managing out-of-order retirement of instructions based on received...

Prime and probe attack mitigation

Managing power in an integrated circuit for high-speed activation

System and method for implementing strong load ordering in a proces...

Methods and systems for distributing memory requests

Noisy instructions for side-channel attack mitigation

System and method for implementing strong load ordering in a proces...

Shared mid-level data cache

Managing load and store instructions for memory barrier handling

Vector prefetching for computing systems

Prime and probe attack mitigation

External way allocation circuitry for processor cores

Managing prefetch lookahead distance based on memory access latency

Differential cache block sizing for computing systems

Pipelines for secure multithread execution

Managing low-level instructions and core interactions in multi-core...

Partitioning in a processor cache

Dynamic designation of instructions as sensitive for constraining m...

System and method for implementing strong load ordering in a proces...

Microarchitectural sensitive tag flow

Managing processor core synchronization using interrupts

Managing out-of-order retirement of instructions

Methods and systems for distributing memory requests

Managing potential faults for speculative page table access

History table management for a correlated prefetcher

Shared mid-level data cache

Mid-level instruction cache

Patents Applicationslast 30 patents

PAGE TABLE ENTRY CACHES WITH MULTIPLE TAG LENGTHS

Error Management In System On A Chip With Securely Partitioned Memo...

Managing Power in an Integrated Circuit for High-Speed Activation

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

System and Method for Implementing Strong Load Ordering in a Proces...

Processor Power Management Using Instruction Throttling

Pipelines for Secure Multithread Execution

Dynamic Designation of Instructions as Sensitive for Constraining I...

System and Method for Implementing Strong Load Ordering in a Proces...

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

Dynamic Designation of Instructions as Sensitive

Pipelines for Secure Multithread Execution

Managing Power in an Integrated Circuit for High-Speed Activation

Managing Commit Order for an External Instruction Relative to Queue...

Managing Load and Store Instructions for Memory Barrier Handling

Managing Trace Information Storage Using Pipeline Instruction Inser...

METHODS AND SYSTEMS FOR DISTRIBUTING MEMORY REQUESTS

Managing Translation Lookaside Buffer Entries Based on Associativit...

PREFETCHING DATA TO REDUCE CACHE MISSES

MANAGING PIPELINE INSTRUCTION INSERTION FOR RECEIVED EXTERNAL INSTR...

MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE...

Preventing Information Leakage In Out-Of-Order Machines Due To Miss...

MANAGING OBSCURED BRANCH PREDICTION INFORMATION

MANAGING BRANCH PREDICTION INFORMATION FOR DIFFERENT CONTEXTS

MANAGING PREDICTOR SELECTION FOR BRANCH PREDICTION

LOCAL INSTRUCTION ORDERING BASED ON MEMORY DOMAINS

MANAGING CACHE PARTITIONS BASED ON CACHE USAGE INFORMATION

MANAGING MEMORY ACCESS REQUESTS WITH PREFETCH FOR STREAMS

MANAGING LOCK AND UNLOCK OPERATIONS USING TRAFFIC PRIORITIZATION

MANAGING LOCK AND UNLOCK OPERATIONS USING OPERATION PREDICTION