Shunichi Saito

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for configurable memory array bank architec...
- Patent number 12,182,397
- Issue date Dec 31, 2024
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with multiple sets of latencies and methods for oper...
- Patent number 11,914,874
- Issue date Feb 27, 2024
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for configurable memory array bank architec...
- Patent number 11,698,726
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for configurable memory array bank architec...
- Patent number 11,209,981
- Issue date Dec 28, 2021
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with multiple sets of latencies and methods for oper...
- Patent number 11,150,821
- Issue date Oct 19, 2021
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with multiple sets of latencies and methods for oper...
- Patent number 10,976,945
- Issue date Apr 13, 2021
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for configurable memory array bank architec...
- Patent number 10,788,985
- Issue date Sep 29, 2020
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices with multiple sets of latencies and methods for oper...
- Patent number 10,481,819
- Issue date Nov 19, 2019
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for configurable memory array bank architec...
- Patent number 10,372,330
- Issue date Aug 6, 2019
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a memory device with dual common data I...
- Patent number 10,049,722
- Issue date Aug 14, 2018
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 9,837,137
- Issue date Dec 5, 2017
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for a memory device with dual common data I...
- Patent number 9,805,786
- Issue date Oct 31, 2017
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 9,368,185
- Issue date Jun 14, 2016
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Load reduced memory module and memory system including the same
- Patent number 8,422,263
- Issue date Apr 16, 2013
- Elpida Memory, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-layer printed wiring board
- Patent number 8,198,549
- Issue date Jun 12, 2012
- Elpida Memory, Inc.
- Shunichi Saito
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low noise semiconductor device
- Patent number 7,986,037
- Issue date Jul 26, 2011
- Hitachi, Ltd.
- Yutaka Uematsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory module
- Patent number 7,440,289
- Issue date Oct 21, 2008
- Elpida Memory, Inc.
- Toshio Sugano
- G11 - INFORMATION STORAGE
Information Patent Grant
Fluid connector
- Patent number 5,494,073
- Issue date Feb 27, 1996
- Nitto Kohki Co., Ltd.
- Shunichi Saito
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information Patent Grant
Pipe coupling
- Patent number 5,343,892
- Issue date Sep 6, 1994
- Nitto Kohki Co., Ltd.
- Shunichi Saito
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...
- Publication number 20250085847
- Publication date Mar 13, 2025
- Lodestar Licensing Group LLC
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...
- Publication number 20240184467
- Publication date Jun 6, 2024
- Lodestar Licensing Group LLC
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR TRAINING OPERATIONS
- Publication number 20240078173
- Publication date Mar 7, 2024
- Micron Technology, Inc.
- OSAMU NAGASHIMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR GENERATING CLOCK SIGNALS
- Publication number 20240038289
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Osamu NAGASHIMA
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...
- Publication number 20230418471
- Publication date Dec 28, 2023
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...
- Publication number 20220187988
- Publication date Jun 16, 2022
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...
- Publication number 20210357137
- Publication date Nov 18, 2021
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...
- Publication number 20210149565
- Publication date May 20, 2021
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...
- Publication number 20200004420
- Publication date Jan 2, 2020
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...
- Publication number 20190369894
- Publication date Dec 5, 2019
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...
- Publication number 20190129637
- Publication date May 2, 2019
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...
- Publication number 20190129635
- Publication date May 2, 2019
- Micron Technology, Inc.
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR A MEMORY DEVICE WITH DUAL COMMON DATA I...
- Publication number 20180197595
- Publication date Jul 12, 2018
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20160267962
- Publication date Sep 15, 2016
- Micron Technology, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC APPARATUS
- Publication number 20160139636
- Publication date May 19, 2016
- Kabushiki Kaisha Toshiba
- Shunichi SAITO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20150098289
- Publication date Apr 9, 2015
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20130215659
- Publication date Aug 22, 2013
- Elpida Memory, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
INFORMATION PROCESSING APPARATUS AND METHOD
- Publication number 20120249600
- Publication date Oct 4, 2012
- Kabushiki Kaisha Toshiba
- Shuji MIYAMOTO
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
ELECTRONIC DEVICE
- Publication number 20110205150
- Publication date Aug 25, 2011
- Kabushiki Kaisha Toshiba
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
Load reduced memory module
- Publication number 20100312925
- Publication date Dec 9, 2010
- Elpida Memory, Inc.
- Fumiyuki Osanai
- G11 - INFORMATION STORAGE
Information Patent Application
Load reduced memory module and memory system including the same
- Publication number 20100309706
- Publication date Dec 9, 2010
- Elpida Memory, Inc.
- Shunichi Saito
- G11 - INFORMATION STORAGE
Information Patent Application
Load reduced memory module
- Publication number 20100312956
- Publication date Dec 9, 2010
- Elpida Memory, Inc.
- Atsushi Hiraishi
- G11 - INFORMATION STORAGE
Information Patent Application
Low noise semiconductor device
- Publication number 20080290495
- Publication date Nov 27, 2008
- Hitachi, Ltd.
- Yutaka Uematsu
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Multi-layer printed wiring board
- Publication number 20080164058
- Publication date Jul 10, 2008
- ELPIDA MEMORY, INC.
- Shunichi Saito
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory module
- Publication number 20080123303
- Publication date May 29, 2008
- Elpida Memory, Inc.
- Toshio Sugano
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Shunichi Saito

Person

Patents Grantslast 30 patents

Apparatuses and methods for configurable memory array bank architec...

Memory devices with multiple sets of latencies and methods for oper...

Apparatuses and methods for configurable memory array bank architec...

Apparatuses and methods for configurable memory array bank architec...

Memory devices with multiple sets of latencies and methods for oper...

Memory devices with multiple sets of latencies and methods for oper...

Apparatuses and methods for configurable memory array bank architec...

Memory devices with multiple sets of latencies and methods for oper...

Apparatuses and methods for configurable memory array bank architec...

Apparatuses and methods for a memory device with dual common data I...

Semiconductor device

Apparatuses and methods for a memory device with dual common data I...

Semiconductor device

Load reduced memory module and memory system including the same

Multi-layer printed wiring board

Low noise semiconductor device

Memory module

Fluid connector

Pipe coupling

Patents Applicationslast 30 patents

APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...

MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...

APPARATUSES AND METHODS FOR TRAINING OPERATIONS

APPARATUSES AND METHODS FOR GENERATING CLOCK SIGNALS

APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...

APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...

MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...

APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...

APPARATUSES AND METHODS FOR CONFIGURABLE MEMORY ARRAY BANK ARCHITEC...

MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...

MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...

MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPER...

APPARATUSES AND METHODS FOR A MEMORY DEVICE WITH DUAL COMMON DATA I...

SEMICONDUCTOR DEVICE

ELECTRONIC APPARATUS

SEMICONDUCTOR DEVICE

LOAD REDUCED MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME

INFORMATION PROCESSING APPARATUS AND METHOD

ELECTRONIC DEVICE

Load reduced memory module

Load reduced memory module and memory system including the same

Load reduced memory module

Low noise semiconductor device

Multi-layer printed wiring board

Memory module