Shwetal A. Patel

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
DDR5 client PMIC power up sequence and state transitions
- Patent number 11,815,978
- Issue date Nov 14, 2023
- RENESAS ELECTRONICS AMERICA INC.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR5 client PMIC power up sequence and state transitions
- Patent number 11,249,539
- Issue date Feb 15, 2022
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR5 RCD interface protocol and operation
- Patent number 10,776,293
- Issue date Sep 15, 2020
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR5 PMIC interface protocol and operation
- Patent number 10,769,082
- Issue date Sep 8, 2020
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register clock driver for DDR5 memory
- Patent number 10,401,899
- Issue date Sep 3, 2019
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced data buffer and intelligent NV controller for simultaneous...
- Patent number 10,394,460
- Issue date Aug 27, 2019
- Integrated Device Technology, Inc.
- Shwetal Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronization of data transmission with a clock signal after a me...
- Patent number 9,847,112
- Issue date Dec 19, 2017
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory includes transmitter for data synchronization transmission a...
- Patent number 9,552,870
- Issue date Jan 24, 2017
- INTEGRATED DEVICE TECHNOLGY, INC.
- Shwetal Arvind Patel
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reducing simultaneous switching outputs using data bus inversion si...
- Patent number 8,260,992
- Issue date Sep 4, 2012
- Advanced Micro Devices, Inc.
- Glenn A. Dearth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent memory buffer
- Patent number 8,019,921
- Issue date Sep 13, 2011
- GLOBALFOUNDRIES, INC.
- Shwetal A. Patel
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System including a host connected to a plurality of memory modules...
- Patent number 7,421,525
- Issue date Sep 2, 2008
- Advanced Micro Devices, Inc.
- R. Stephen Polzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM supporting different burst-length accesses without changing th...
- Patent number 6,957,308
- Issue date Oct 18, 2005
- Advanced Micro Devices, Inc.
- Shwetal Patel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
WRITE PROTECT FUNCTION WITH SECURE CERTIFICATE AUTHENTICATION
- Publication number 20230394160
- Publication date Dec 7, 2023
- Renesas Electronics America Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS
- Publication number 20220197366
- Publication date Jun 23, 2022
- Renesas Electronics America Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS
- Publication number 20200409446
- Publication date Dec 31, 2020
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR5 PMIC INTERFACE PROTOCOL AND OPERATION
- Publication number 20190340142
- Publication date Nov 7, 2019
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR5 RCD INTERFACE PROTOCOL AND OPERATION
- Publication number 20190340141
- Publication date Nov 7, 2019
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER CLOCK DRIVER FOR DDR5 MEMORY
- Publication number 20170344051
- Publication date Nov 30, 2017
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION AFTER A MEMORY MODE SWITCH
- Publication number 20170256295
- Publication date Sep 7, 2017
- Integrated Device Technology, Inc.
- Shwetal Arvind Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY CONTROL
- Publication number 20120239887
- Publication date Sep 20, 2012
- Advanced Micro Devices, Inc.
- James R. MAGRO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SI...
- Publication number 20110252171
- Publication date Oct 13, 2011
- Glenn A. Dearth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTELLIGENT MEMORY BUFFER
- Publication number 20100125681
- Publication date May 20, 2010
- Shwetal A. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE
- Publication number 20090091963
- Publication date Apr 9, 2009
- Advanced Micro Devices, Inc.
- Shwetal A. Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System including a host connected serially in a chain to one or mor...
- Publication number 20050166006
- Publication date Jul 28, 2005
- Advanced Micro Devices, Inc.
- Gerald R. Talbot
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System including a host connected to a plurality of memory modules...
- Publication number 20040230718
- Publication date Nov 18, 2004
- Advanced Micro Devices, Inc.
- R. Stephen Polzin
- G06 - COMPUTING CALCULATING COUNTING

Shwetal A. Patel

Person

Patents Grantslast 30 patents

DDR5 client PMIC power up sequence and state transitions

DDR5 client PMIC power up sequence and state transitions

DDR5 RCD interface protocol and operation

DDR5 PMIC interface protocol and operation

Register clock driver for DDR5 memory

Enhanced data buffer and intelligent NV controller for simultaneous...

Synchronization of data transmission with a clock signal after a me...

Memory includes transmitter for data synchronization transmission a...

Reducing simultaneous switching outputs using data bus inversion si...

Intelligent memory buffer

System including a host connected to a plurality of memory modules...

DRAM supporting different burst-length accesses without changing th...

Patents Applicationslast 30 patents

WRITE PROTECT FUNCTION WITH SECURE CERTIFICATE AUTHENTICATION

DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS

DDR5 CLIENT PMIC POWER UP SEQUENCE AND STATE TRANSITIONS

DDR5 PMIC INTERFACE PROTOCOL AND OPERATION

DDR5 RCD INTERFACE PROTOCOL AND OPERATION

REGISTER CLOCK DRIVER FOR DDR5 MEMORY

SYNCHRONIZATION AFTER A MEMORY MODE SWITCH

METHOD AND APPARATUS FOR MEMORY CONTROL

REDUCING SIMULTANEOUS SWITCHING OUTPUTS USING DATA BUS INVERSION SI...

INTELLIGENT MEMORY BUFFER

MEMORY DEVICE

System including a host connected serially in a chain to one or mor...

System including a host connected to a plurality of memory modules...