Shyam Sunder Raghunathan

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Transient and stable state read operations of a memory device
- Patent number 12,224,016
- Issue date Feb 11, 2025
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Wordline or pillar state detection for faster read access times
- Patent number 12,205,653
- Issue date Jan 21, 2025
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial block erase operations in memory devices
- Patent number 12,087,372
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Storing highly read data at low impact read disturb pages of a memo...
- Patent number 11,762,767
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250226034
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONFIGURED TO RESUME A SUSPENDED ERASE OPERATION WITH A VARI...
- Publication number 20250210116
- Publication date Jun 26, 2025
- Micron Technology, Inc.
- Kannan Abinaya
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE
- Publication number 20250157549
- Publication date May 15, 2025
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE...
- Publication number 20250140323
- Publication date May 1, 2025
- Micron Technology, Inc.
- Xiangang Luo
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20250140322
- Publication date May 1, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE OR PILLAR STATE DETECTION FOR FASTER READ ACCESS TIMES
- Publication number 20250104781
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20250087275
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
RESUMING SUSPENDED PROGRAM OPERATIONS IN A MEMORY DEVICE
- Publication number 20250004789
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Keng Gee Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS
- Publication number 20250006275
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES
- Publication number 20250006292
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Taylor Alu
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM
- Publication number 20250006269
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Yu-Chung Lien
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES
- Publication number 20240379176
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE
- Publication number 20240339163
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Leo Raimondo
- G11 - INFORMATION STORAGE
Information Patent Application
CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE
- Publication number 20240312529
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Karan Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20240168880
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20240168878
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...
- Publication number 20240168879
- Publication date May 23, 2024
- Micron Technology, Inc.
- Akira Goda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE
- Publication number 20240062829
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE OR PILLAR STATE DETECTION FOR FASTER READ ACCESS TIMES
- Publication number 20230197169
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES
- Publication number 20220415414
- Publication date Dec 29, 2022
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Application
STORING HIGHLY READ DATA AT LOW IMPACT READ DISTURB PAGES OF A MEMO...
- Publication number 20220342813
- Publication date Oct 27, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Shyam Sunder Raghunathan

Person

Patents Grantslast 30 patents

Transient and stable state read operations of a memory device

Wordline or pillar state detection for faster read access times

Partial block erase operations in memory devices

Storing highly read data at low impact read disturb pages of a memo...

Patents Applicationslast 30 patents

PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

MEMORY CONFIGURED TO RESUME A SUSPENDED ERASE OPERATION WITH A VARI...

TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE

LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE...

SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

WORDLINE OR PILLAR STATE DETECTION FOR FASTER READ ACCESS TIMES

SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

RESUMING SUSPENDED PROGRAM OPERATIONS IN A MEMORY DEVICE

SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS

STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES

MANAGING ALLOCATION OF BLOCKS IN A MEMORY SUB-SYSTEM

PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES

BOOST-BY-DECK DURING A PROGRAM OPERATION ON A MEMORY DEVICE

CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE

READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

READ DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME...

TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE

WORDLINE OR PILLAR STATE DETECTION FOR FASTER READ ACCESS TIMES

PARTIAL BLOCK ERASE OPERATIONS IN MEMORY DEVICES

STORING HIGHLY READ DATA AT LOW IMPACT READ DISTURB PAGES OF A MEMO...