Shyam Sunder Raghunathan

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 10,658,053
- Issue date May 19, 2020
- Intel Corporation
- Shantanu R Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming memories with multi-level pass signal
- Patent number 10,043,574
- Issue date Aug 7, 2018
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming memories with multi-level pass signal
- Patent number 9,922,704
- Issue date Mar 20, 2018
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 9,792,997
- Issue date Oct 17, 2017
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Defect management policies for NAND flash memory
- Patent number 9,535,777
- Issue date Jan 3, 2017
- Intel Corporation
- Pranav Kalavade
- G11 - INFORMATION STORAGE
Information Patent Grant
Ramping inhibit voltage during memory programming
- Patent number 9,418,752
- Issue date Aug 16, 2016
- Intel Corporation
- Shantanu R Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically compensating for degradation of a non-volatile memory d...
- Patent number 9,418,000
- Issue date Aug 16, 2016
- Intel Corporation
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming memories with multi-level pass signal
- Patent number 9,396,791
- Issue date Jul 19, 2016
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-pulse programming for memory
- Patent number 9,245,645
- Issue date Jan 26, 2016
- Intel Corporation
- Charan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Program VT spread folding for NAND flash memory programming
- Patent number 9,099,183
- Issue date Aug 4, 2015
- Intel Corporation
- Charan Srinivasan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
- Publication number 20180190347
- Publication date Jul 5, 2018
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
- Publication number 20180122487
- Publication date May 3, 2018
- Intel Corporation
- Shantanu R. RAJWADE
- G11 - INFORMATION STORAGE
Information Patent Application
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
- Publication number 20160372207
- Publication date Dec 22, 2016
- Intel Corporation
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
- Publication number 20160307622
- Publication date Oct 20, 2016
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY D...
- Publication number 20160180958
- Publication date Jun 23, 2016
- Intel Corporation
- SHYAM SUNDER RAGHUNATHAN
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL
- Publication number 20160019949
- Publication date Jan 21, 2016
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING
- Publication number 20150279476
- Publication date Oct 1, 2015
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAM VT SPREAD FOLDING FOR NAND FLASH MEMORY PROGRAMMING
- Publication number 20150179267
- Publication date Jun 25, 2015
- Charan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
DEFECT MANAGEMENT POLICIES FOR NAND FLASH MEMORY
- Publication number 20150149818
- Publication date May 28, 2015
- Pranav Kalavade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PULSE PROGRAMMING FOR MEMORY
- Publication number 20150043275
- Publication date Feb 12, 2015
- Charan Srinivasan
- G11 - INFORMATION STORAGE

Shyam Sunder Raghunathan

Person

Patents Grantslast 30 patents

Ramping inhibit voltage during memory programming

Programming memories with multi-level pass signal

Programming memories with multi-level pass signal

Ramping inhibit voltage during memory programming

Defect management policies for NAND flash memory

Ramping inhibit voltage during memory programming

Dynamically compensating for degradation of a non-volatile memory d...

Programming memories with multi-level pass signal

Multi-pulse programming for memory

Program VT spread folding for NAND flash memory programming

Patents Applicationslast 30 patents

PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL

RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING

RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING

PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL

DYNAMICALLY COMPENSATING FOR DEGRADATION OF A NON-VOLATILE MEMORY D...

PROGRAMMING MEMORIES WITH MULTI-LEVEL PASS SIGNAL

RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING

PROGRAM VT SPREAD FOLDING FOR NAND FLASH MEMORY PROGRAMMING

DEFECT MANAGEMENT POLICIES FOR NAND FLASH MEMORY

MULTI-PULSE PROGRAMMING FOR MEMORY