Siddharth Alur

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
High density organic interconnect structures
- Patent number 12,062,551
- Issue date Aug 13, 2024
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,935,805
- Issue date Mar 19, 2024
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,664,290
- Issue date May 30, 2023
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 11,631,595
- Issue date Apr 18, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer solution based deposition of dielectrics for advanced s...
- Patent number 11,508,636
- Issue date Nov 22, 2022
- Intel Corporation
- Andrew Brown
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of tall metal pillars using multiple photoresist layers
- Patent number 11,393,762
- Issue date Jul 19, 2022
- Intel Corporation
- Sri Chaitra J. Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 11,195,727
- Issue date Dec 7, 2021
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low z-height, ultra-low dielectric constant air cavity based and mu...
- Patent number 11,196,165
- Issue date Dec 7, 2021
- Intel Corporation
- Sri Chaitra Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,158,558
- Issue date Oct 26, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package substrate having polymer-derived ceramic core
- Patent number 11,075,130
- Issue date Jul 27, 2021
- Intel Corporation
- Lisa Ying Ying Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical interconnections with improved compliance due to stress...
- Patent number 10,903,137
- Issue date Jan 26, 2021
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plated through hole socketing coupled to a solder ball to engage wi...
- Patent number 10,741,947
- Issue date Aug 11, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device including non-homogeneous build-up dielectric
- Patent number 10,727,184
- Issue date Jul 28, 2020
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 10,685,850
- Issue date Jun 16, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for semiconductor packages using photoimageable...
- Patent number 10,553,453
- Issue date Feb 4, 2020
- Intel Corporation
- Sri Chaitra Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical interconnections with improved compliance due to stress...
- Patent number 10,424,530
- Issue date Sep 24, 2019
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming a substrate structure for an electrical compone...
- Patent number 10,384,431
- Issue date Aug 20, 2019
- Intel Corporation
- Ji Yong Park
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High resolution solder resist material for silicon bridge application
- Patent number 10,020,262
- Issue date Jul 10, 2018
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit surface layer with adhesion-functional group
- Patent number 9,728,500
- Issue date Aug 8, 2017
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20240355641
- Publication date Oct 24, 2024
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20240186202
- Publication date Jun 6, 2024
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED PASSIVES WITH CAVITY SIDEWALL INTERCONNECT IN GLASS CORE A...
- Publication number 20240114622
- Publication date Apr 4, 2024
- Intel Corporation
- Kristof Darmawikarta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE TRACE WIDTH IN MULTI-LAYER SUBSTRATE PACKAGE
- Publication number 20240070366
- Publication date Feb 29, 2024
- Intel Corporation
- Nicholas HAEHN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20230245940
- Publication date Aug 3, 2023
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20230223278
- Publication date Jul 13, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETIC INDUCTOR DEVICE AND METHOD
- Publication number 20230092492
- Publication date Mar 23, 2023
- Intel Corporation
- Xin Ning
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20220059367
- Publication date Feb 24, 2022
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210391232
- Publication date Dec 16, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210111088
- Publication date Apr 15, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LITHOGRAPHICALLY DEFINED VERTICAL INTERCONNECT ACCESS (VIA) FOR A B...
- Publication number 20200411441
- Publication date Dec 31, 2020
- Intel Corporation
- Kristof DARMAWIKARTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20200312675
- Publication date Oct 1, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE INCLUDING NON-HOMOGENEOUS BUILD-UP DIELECTRIC
- Publication number 20200105673
- Publication date Apr 2, 2020
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER SOLUTION BASED DEPOSITION OF DIELECTRICS FOR ADVANCED S...
- Publication number 20200006180
- Publication date Jan 2, 2020
- Intel Corporation
- Andrew BROWN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE SUBSTRATE HAVING POLYMER-DERIVED CERAMIC CORE
- Publication number 20190393109
- Publication date Dec 26, 2019
- Intel Corporation
- Lisa Ying Ying CHEN
- C04 - CEMENTS CONCRETE ARTIFICIAL STONE CERAMICS REFRACTORIES
Information Patent Application
LOW Z-HEIGHT, ULTRA-LOW DIELECTRIC CONSTANT AIR CAVITY BASED AND MU...
- Publication number 20190393606
- Publication date Dec 26, 2019
- Intel Corporation
- Sri Chaitra CHAVALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL INTERCONNECTIONS WITH IMPROVED COMPLIANCE DUE TO STRESS...
- Publication number 20190393129
- Publication date Dec 26, 2019
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF TALL METAL PILLARS USING MULTIPLE PHOTORESIST LAYERS
- Publication number 20190326222
- Publication date Oct 24, 2019
- Intel Corporation
- Sri Chaitra J. Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEMS AND METHODS FOR SEMICONDUCTOR PACKAGES USING PHOTOIMAGEABLE...
- Publication number 20190311916
- Publication date Oct 10, 2019
- Intel Corporation
- Sri Chaitra CHAVALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20190221447
- Publication date Jul 18, 2019
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLATED THROUGH HOLE SOCKETING
- Publication number 20190214751
- Publication date Jul 11, 2019
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for forming a substrate structure for an electrical compone...
- Publication number 20180281374
- Publication date Oct 4, 2018
- Intel Corporation
- Ji Yong Park
- B32 - LAYERED PRODUCTS
Information Patent Application
HIGH RESOLUTION SOLDER RESIST MATERIAL FOR SILICON BRIDGE APPLICATION
- Publication number 20180005946
- Publication date Jan 4, 2018
- Intel Corporation
- SIDDHARTH K. ALUR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP
- Publication number 20170301619
- Publication date Oct 19, 2017
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS TOLERANT COMPOSITE MATERIAL AND ARCHITECTURE
- Publication number 20170174894
- Publication date Jun 22, 2017
- Sri Chaitra Chavali
- C09 - DYES PAINTS POLISHES NATURAL RESINS ADHESIVES MISCELLANEOUS COMPOSITION...
Information Patent Application
INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP
- Publication number 20170179019
- Publication date Jun 22, 2017
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS

Siddharth Alur

Person

Patents Grantslast 30 patents

High density organic interconnect structures

Package with underfill containment barrier

Package with underfill containment barrier

High density organic interconnect structures

Multi-layer solution based deposition of dielectrics for advanced s...

Formation of tall metal pillars using multiple photoresist layers

High density organic interconnect structures

Low z-height, ultra-low dielectric constant air cavity based and mu...

Package with underfill containment barrier

Package substrate having polymer-derived ceramic core

Electrical interconnections with improved compliance due to stress...

Plated through hole socketing coupled to a solder ball to engage wi...

Microelectronic device including non-homogeneous build-up dielectric

High density organic interconnect structures

Systems and methods for semiconductor packages using photoimageable...

Electrical interconnections with improved compliance due to stress...

Methods for forming a substrate structure for an electrical compone...

High resolution solder resist material for silicon bridge application

Integrated circuit surface layer with adhesion-functional group

Patents Applicationslast 30 patents

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

EMBEDDED PASSIVES WITH CAVITY SIDEWALL INTERCONNECT IN GLASS CORE A...

ADAPTIVE TRACE WIDTH IN MULTI-LAYER SUBSTRATE PACKAGE

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

MAGNETIC INDUCTOR DEVICE AND METHOD

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

LITHOGRAPHICALLY DEFINED VERTICAL INTERCONNECT ACCESS (VIA) FOR A B...

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

MICROELECTRONIC DEVICE INCLUDING NON-HOMOGENEOUS BUILD-UP DIELECTRIC

MULTI-LAYER SOLUTION BASED DEPOSITION OF DIELECTRICS FOR ADVANCED S...

PACKAGE SUBSTRATE HAVING POLYMER-DERIVED CERAMIC CORE

LOW Z-HEIGHT, ULTRA-LOW DIELECTRIC CONSTANT AIR CAVITY BASED AND MU...

ELECTRICAL INTERCONNECTIONS WITH IMPROVED COMPLIANCE DUE TO STRESS...

FORMATION OF TALL METAL PILLARS USING MULTIPLE PHOTORESIST LAYERS

SYSTEMS AND METHODS FOR SEMICONDUCTOR PACKAGES USING PHOTOIMAGEABLE...

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

PLATED THROUGH HOLE SOCKETING

Methods for forming a substrate structure for an electrical compone...

HIGH RESOLUTION SOLDER RESIST MATERIAL FOR SILICON BRIDGE APPLICATION

INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP

STRESS TOLERANT COMPOSITE MATERIAL AND ARCHITECTURE

INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP