Siegmar Koeppe

Person

Munich, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Identification circuit and method for generating an identification bit
- Patent number 8,854,866
- Issue date Oct 7, 2014
- Infineon Technologies AG
- Peter Huber
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Latch based memory device
- Patent number 8,780,648
- Issue date Jul 15, 2014
- Infineon Technologies AG
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory reliability verification techniques
- Patent number 8,605,526
- Issue date Dec 10, 2013
- Infineon Technologies AG
- Peter Huber
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch based memory device
- Patent number 8,331,163
- Issue date Dec 11, 2012
- Infineon Technologies AG
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and system with a time delay path and method for propagat...
- Patent number 8,243,555
- Issue date Aug 14, 2012
- Infineon Technologies AG
- Stephan Henzler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and device for controlling a memory access and corresponding...
- Patent number 8,223,573
- Issue date Jul 17, 2012
- Infineon Technologies AG
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Grant
Data moving processor
- Patent number 8,209,523
- Issue date Jun 26, 2012
- Intel Mobile Communications GmbH
- Ulf Nordqvist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Divider circuit
- Patent number 7,656,204
- Issue date Feb 2, 2010
- Infineon Technologies AG
- Stephan Henzler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit arrangement for supplying configuration data in FPGA devices
- Patent number 7,492,187
- Issue date Feb 17, 2009
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mask-programmable logic macro and method for programming a logic macro
- Patent number 7,439,765
- Issue date Oct 21, 2008
- Infineon Technologies AG
- Winfried Kamp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shift register for safely providing a configuration bit
- Patent number 7,177,385
- Issue date Feb 13, 2007
- Infineon Technologies AG
- Georg Georgakos
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing method for semiconductor circuit levels
- Patent number 5,610,531
- Issue date Mar 11, 1997
- Siemens Aktiengesellschaft
- Werner Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for simulating an open fault in a logic circuit comprising f...
- Patent number 4,868,825
- Issue date Sep 19, 1989
- Siemens Aktiengesellschaft
- Siegmar Koeppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for simulating a fault in a logic circuit and a simulation m...
- Patent number 4,852,093
- Issue date Jul 25, 1989
- Siemens Aktiengesellschaft
- Siegmar Koeppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Monolithic integrated circuit comprising circuit branches parallel...
- Patent number 4,799,096
- Issue date Jan 17, 1989
- Siemens Aktiengesellschaft
- Siegmar Koeppe
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Latch Based Memory Device
- Publication number 20130141987
- Publication date Jun 6, 2013
- INFINEON TECHNOLOGIES AG
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY RELIABILITY VERIFICATION TECHNIQUES
- Publication number 20120307579
- Publication date Dec 6, 2012
- INFINEON TECHNOLOGIES AG
- Peter Huber
- G11 - INFORMATION STORAGE
Information Patent Application
Latch Based Memory Device
- Publication number 20120057411
- Publication date Mar 8, 2012
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Application
Identification Circuit and Method for Generating an Identification Bit
- Publication number 20120020145
- Publication date Jan 26, 2012
- INFINEON TECHNOLOGIES AG
- Peter Huber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus And System With A Time DelayApparatus And System With A T...
- Publication number 20100034056
- Publication date Feb 11, 2010
- INFINEON TECHNOLOGIES AG
- Stephan HENZLER
- G04 - HOROLOGY
Information Patent Application
Method and device for controlling a memory access and corresponding...
- Publication number 20090213674
- Publication date Aug 27, 2009
- INFINEON TECHNOLOGIES AG
- Siegmar Koeppe
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable logic cell, configurable cell, configurable cell arran...
- Publication number 20080079460
- Publication date Apr 3, 2008
- Infineon Technologies AG
- Francisco-Javier Veredas-Ramirez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Divider circuit
- Publication number 20070216451
- Publication date Sep 20, 2007
- Infineon Technologies AG
- Stephan Henzler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Carry-ripple adder
- Publication number 20060294178
- Publication date Dec 28, 2006
- Marc Bernhardt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mask-programmable logic macro and method for programming a logic macro
- Publication number 20060279329
- Publication date Dec 14, 2006
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit arrangement for supplying configuration data in FPGA devices
- Publication number 20060273823
- Publication date Dec 7, 2006
- Infineon Technologies AG
- Winfried Kamp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Shift register for safely providing a configuration bit
- Publication number 20050163277
- Publication date Jul 28, 2005
- Infineon Technologies AG
- Georg Georgakos
- H03 - BASIC ELECTRONIC CIRCUITRY

Siegmar Koeppe

Person

Patents Grantslast 30 patents

Identification circuit and method for generating an identification bit

Latch based memory device

Memory reliability verification techniques

Latch based memory device

Apparatus and system with a time delay path and method for propagat...

Method and device for controlling a memory access and corresponding...

Data moving processor

Divider circuit

Circuit arrangement for supplying configuration data in FPGA devices

Mask-programmable logic macro and method for programming a logic macro

Shift register for safely providing a configuration bit

Testing method for semiconductor circuit levels

Method for simulating an open fault in a logic circuit comprising f...

Method for simulating a fault in a logic circuit and a simulation m...

Monolithic integrated circuit comprising circuit branches parallel...

Patents Applicationslast 30 patents

Latch Based Memory Device

MEMORY RELIABILITY VERIFICATION TECHNIQUES

Latch Based Memory Device

Identification Circuit and Method for Generating an Identification Bit

Apparatus And System With A Time DelayApparatus And System With A T...

Method and device for controlling a memory access and corresponding...

Programmable logic cell, configurable cell, configurable cell arran...

Divider circuit

Carry-ripple adder

Mask-programmable logic macro and method for programming a logic macro

Circuit arrangement for supplying configuration data in FPGA devices

Shift register for safely providing a configuration bit