Sih-Jie Liu

Person

Hsinchu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method and device to reduce epitaxial defects due to contact stress...
- Patent number 12,283,515
- Issue date Apr 22, 2025
- Taiwan Semiconductor Manufacturing Company Limited
- Sih-Jie Liu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Reduce well dopant loss in FinFETs through co-implantation
- Patent number 11,978,634
- Issue date May 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce well dopant loss in FinFETs through co-implantation
- Patent number 11,348,792
- Issue date May 31, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce well dopant loss in FinFETs through co-implantation
- Patent number 10,930,507
- Issue date Feb 23, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
- Publication number 20250169132
- Publication date May 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chang LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20250126859
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chang LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTOR WITH RECRYSTALLIZED SOURCE/DRAINS AND METHOD
- Publication number 20250113551
- Publication date Apr 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chia-Cheng CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCE WELL DOPANT LOSS IN FINFETS THROUGH CO-IMPLANTATION
- Publication number 20240249944
- Publication date Jul 25, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE
- Publication number 20230387251
- Publication date Nov 30, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tien-Shun CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduce Well Dopant Loss in FinFETs Through Co-Implantation
- Publication number 20220301874
- Publication date Sep 22, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND DEVICE TO REDUCE EPITAXIAL DEFECTS DUE TO CONTACT STRESS...
- Publication number 20220059394
- Publication date Feb 24, 2022
- Taiwan Semiconductor Manufacturing Company Limited
- Sih-Jie LIU
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Reduce Well Dopant Loss in FinFETs Through Co-Implantation
- Publication number 20210202253
- Publication date Jul 1, 2021
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduce Well Dopant Loss in FinFETs Through Co-Implantation
- Publication number 20200135469
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sih-Jie Liu
- H01 - BASIC ELECTRIC ELEMENTS

Sih-Jie Liu

Person

Patents Grantslast 30 patents

Method and device to reduce epitaxial defects due to contact stress...

Reduce well dopant loss in FinFETs through co-implantation

Reduce well dopant loss in FinFETs through co-implantation

Reduce well dopant loss in FinFETs through co-implantation

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

FIELD EFFECT TRANSISTOR WITH RECRYSTALLIZED SOURCE/DRAINS AND METHOD

REDUCE WELL DOPANT LOSS IN FINFETS THROUGH CO-IMPLANTATION

GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE

Reduce Well Dopant Loss in FinFETs Through Co-Implantation

METHOD AND DEVICE TO REDUCE EPITAXIAL DEFECTS DUE TO CONTACT STRESS...

Reduce Well Dopant Loss in FinFETs Through Co-Implantation

Reduce Well Dopant Loss in FinFETs Through Co-Implantation