Silke Penth

Person

Holzgerlingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Field-effect transistor placement optimization for improved leaf ce...
- Patent number 10,565,340
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Field-effect transistor placement optimization for improved leaf ce...
- Patent number 10,394,994
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,997,218
- Issue date Jun 12, 2018
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout of interconnect lines in integrated circuits
- Patent number 9,904,754
- Issue date Feb 27, 2018
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of interconnect lines in integrated circuits
- Patent number 9,898,571
- Issue date Feb 20, 2018
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,792,967
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode operation having power saving and active modes in a stack...
- Patent number 9,786,339
- Issue date Oct 10, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing semiconductor memory array leakage current
- Patent number 9,761,289
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Paul A. Bunce
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit
- Patent number 9,711,244
- Issue date Jul 18, 2017
- International Business Machines Corporation
- Yuen H. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,437,285
- Issue date Sep 6, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
Write address synchronization in 2 read/1write SRAM arrays
- Patent number 9,406,375
- Issue date Aug 2, 2016
- International Business Machines Corporation
- Harry Barowski
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM array comprising multiple cell cores
- Patent number 9,384,823
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Michael Kugel
- G11 - INFORMATION STORAGE
Information Patent Grant
Defective memory column replacement with load isolation
- Patent number 8,964,493
- Issue date Feb 24, 2015
- International Business Machines Corporation
- Silke Penth
- G11 - INFORMATION STORAGE
Information Patent Grant
Local evaluation circuit for static random-access memory
- Patent number 8,837,235
- Issue date Sep 16, 2014
- International Business Machines Corporation
- Yuen Hung Chan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...
- Publication number 20180322235
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...
- Publication number 20180322236
- Publication date Nov 8, 2018
- International Business Machines Corporation
- Iris Maria Leefken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20180005674
- Publication date Jan 4, 2018
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...
- Publication number 20170243619
- Publication date Aug 24, 2017
- International Business Machines Corporation
- PAUL A. BUNCE
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170228489
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170228487
- Publication date Aug 10, 2017
- International Business Machines Corporation
- Gerhard Hellner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SRAM ARRAY COMPRISING MULTIPLE CELL CORES
- Publication number 20160086659
- Publication date Mar 24, 2016
- International Business Machines Corporation
- Michael Kugel
- G11 - INFORMATION STORAGE
Information Patent Application
Local Evaluation Circuit for Static Random-Access Memory
- Publication number 20140254290
- Publication date Sep 11, 2014
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Yuen Hung Chan
- G11 - INFORMATION STORAGE
Information Patent Application
DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION
- Publication number 20140192602
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Silke Penth
- G11 - INFORMATION STORAGE

Silke Penth

Person

Patents Grantslast 30 patents

Field-effect transistor placement optimization for improved leaf ce...

Field-effect transistor placement optimization for improved leaf ce...

Dual mode operation having power saving and active modes in a stack...

Layout of interconnect lines in integrated circuits

Layout of interconnect lines in integrated circuits

Managing semiconductor memory array leakage current

Dual mode operation having power saving and active modes in a stack...

Managing semiconductor memory array leakage current

Memory circuit

Write address synchronization in 2 read/1write SRAM arrays

Write address synchronization in 2 read/1write SRAM arrays

SRAM array comprising multiple cell cores

Defective memory column replacement with load isolation

Local evaluation circuit for static random-access memory

Patents Applicationslast 30 patents

FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...

FIELD-EFFECT TRANSISTOR PLACEMENT OPTIMIZATION FOR IMPROVED LEAF CE...

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

DUAL MODE OPERATION HAVING POWER SAVING AND ACTIVE MODES IN A STACK...

LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

LAYOUT OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

SRAM ARRAY COMPRISING MULTIPLE CELL CORES

Local Evaluation Circuit for Static Random-Access Memory

DEFECTIVE MEMORY COLUMN REPLACEMENT WITH LOAD ISOLATION