Simone Bartoli

Person

Milan, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Memory device, memory address decoder, system, and related method f...
- Patent number 11,443,820
- Issue date Sep 13, 2022
- Microchip Technology Incorporated
- Lorenzo Bedarida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Erase techniques and circuits therefor for non-volatile memory devices
- Patent number 9,349,480
- Issue date May 24, 2016
- PS4 Luxco S.A.R.L.
- Vincenzo Ferragina
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming selection transistors for NAND flash memory
- Patent number 8,995,192
- Issue date Mar 31, 2015
- PS4 Luxco S.A.R.L.
- Osama Khouri
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase techniques and circuits therefor for non-volatile memory devices
- Patent number 8,705,283
- Issue date Apr 22, 2014
- Vincenzo Ferragina
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit to discharge bit lines after an erase pulse
- Patent number 8,644,079
- Issue date Feb 4, 2014
- Marco Passerini
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device in particular extra array configured therein for conf...
- Patent number 8,599,615
- Issue date Dec 3, 2013
- Elpida Memory, Inc.
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier
- Patent number 7,920,436
- Issue date Apr 5, 2011
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensated current offset in a sensing circuit
- Patent number 7,782,695
- Issue date Aug 24, 2010
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexible, low cost apparatus and method to introduce and check algo...
- Patent number 7,769,943
- Issue date Aug 3, 2010
- Atmel Corporation
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array architecture with joined word lines
- Patent number 7,684,245
- Issue date Mar 23, 2010
- Atmel Corporation
- Steve Schumann
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense architecture
- Patent number 7,561,485
- Issue date Jul 14, 2009
- Atmel Corporation
- Gabriele Pelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementation of column redundancy for a flash memory with a high...
- Patent number 7,551,498
- Issue date Jun 23, 2009
- Atmel Corporation
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for reducing soft-writing in a multi-level flash...
- Patent number 7,522,455
- Issue date Apr 21, 2009
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for discharging a memory cell in a memory devi...
- Patent number 7,499,334
- Issue date Mar 3, 2009
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase verify method for NAND-type flash memories
- Patent number 7,414,891
- Issue date Aug 19, 2008
- Atmel Corporation
- Stefano Sivero
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for managing address bits during buffered program...
- Patent number 7,404,049
- Issue date Jul 22, 2008
- Atmel Corporation
- Simone Bartoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for regulating a program voltage value during mul...
- Patent number 7,379,338
- Issue date May 27, 2008
- Atmel Corporation
- Massimiliano Frulio
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for a programming approach for a nonvolatile elec...
- Patent number 7,345,921
- Issue date Mar 18, 2008
- Atmel Corporation
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Grant
Column decoding architecture for flash memories
- Patent number 7,333,389
- Issue date Feb 19, 2008
- Atmel Corporation
- Stefano Sivero
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for managing a suspend request in a flash memory
- Patent number 7,302,518
- Issue date Nov 27, 2007
- Atmel Corporation
- Stefano Surico
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for matching resistance in a non-volatile memory
- Patent number 7,283,396
- Issue date Oct 16, 2007
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
System for configuring parameters for a flash memory
- Patent number 7,249,215
- Issue date Jul 24, 2007
- Atmel Corporation
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for regulating a program voltage value during mul...
- Patent number 7,184,311
- Issue date Feb 27, 2007
- Atmel Corporation
- Massimiliano Frulio
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for configuring parameters for flash memory
- Patent number 7,181,565
- Issue date Feb 20, 2007
- Atmel Corporation
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensated method to implement a high voltage discharge phase afte...
- Patent number 7,177,198
- Issue date Feb 13, 2007
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
System for performing fast testing during flash reference cell setting
- Patent number 7,158,415
- Issue date Jan 2, 2007
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Autotesting method of a memory cell matrix, particularly of the non...
- Patent number 6,963,512
- Issue date Nov 8, 2005
- STMicroelectronics S.r.l.
- Antonino Geraci
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with functional capability of simultaneous modi...
- Patent number 6,912,598
- Issue date Jun 28, 2005
- STMicroelectrics S.r.l.
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device with burst mode reading and correspondin...
- Patent number 6,854,040
- Issue date Feb 8, 2005
- STMicroelectronics S.r.l.
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory architecture with page mode erase using NMOS and PMOS...
- Patent number 6,804,148
- Issue date Oct 12, 2004
- Atmel Corporation
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE, MEMORY ADDRESS DECODER, SYSTEM, AND RELATED METHOD F...
- Publication number 20190228831
- Publication date Jul 25, 2019
- MICROCHIP TECHNOLOGY INCORPORATED
- Lorenzo Bedarida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices
- Publication number 20140293707
- Publication date Oct 2, 2014
- Vincenzo Ferragina
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY
- Publication number 20130258780
- Publication date Oct 3, 2013
- Elpida Memory, Inc.
- Osama Khouri
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHO...
- Publication number 20130193590
- Publication date Aug 1, 2013
- Elpida Memory, Inc.
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE IN PARTICULAR EXTRA ARRAY CONFIGURED THEREIN FOR CONF...
- Publication number 20130094295
- Publication date Apr 18, 2013
- Elpida Memory, Inc.
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Application
ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICES
- Publication number 20130016564
- Publication date Jan 17, 2013
- Elpida Memory, Inc.
- Vincenzo Ferragina
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE
- Publication number 20120287723
- Publication date Nov 15, 2012
- Elpida Memory, Inc.
- Marco Passerini
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER
- Publication number 20100149896
- Publication date Jun 17, 2010
- ATMEL CORPORATION
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES
- Publication number 20090109754
- Publication date Apr 30, 2009
- ATMEL CORPORATION
- Steve Schumann
- G11 - INFORMATION STORAGE
Information Patent Application
FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGO...
- Publication number 20080250191
- Publication date Oct 9, 2008
- ATMEL CORPORATION
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES
- Publication number 20080232169
- Publication date Sep 25, 2008
- ATMEL CORPORATION
- Massimiliano Frulio
- G11 - INFORMATION STORAGE
Information Patent Application
Sense architecture
- Publication number 20080170441
- Publication date Jul 17, 2008
- Gabriele Pelli
- G11 - INFORMATION STORAGE
Information Patent Application
Compensated current offset in a sensing circuit
- Publication number 20080170455
- Publication date Jul 17, 2008
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES
- Publication number 20080165585
- Publication date Jul 10, 2008
- ATMEL CORPORATION
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH...
- Publication number 20080144379
- Publication date Jun 19, 2008
- ATMEL CORPORATION
- Simone Bartoli
- G11 - INFORMATION STORAGE
Information Patent Application
System for configuring parameters for a flash memory
- Publication number 20070083699
- Publication date Apr 12, 2007
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for regulating a program voltage value during mul...
- Publication number 20070076476
- Publication date Apr 5, 2007
- Massimiliano Frulio
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for discharging a memory cell in a memory devi...
- Publication number 20070047325
- Publication date Mar 1, 2007
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for matching resistance in a non-volatile memory
- Publication number 20060279988
- Publication date Dec 14, 2006
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for configuring parameters for flash memory
- Publication number 20060253644
- Publication date Nov 9, 2006
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for managing a suspend request in a flash memory
- Publication number 20060161727
- Publication date Jul 20, 2006
- Stefano Surico
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for performing fast testing during flash reference cell setting
- Publication number 20060140030
- Publication date Jun 29, 2006
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for reducing soft-writing in a multi-level flash...
- Publication number 20060140010
- Publication date Jun 29, 2006
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for regulating a program voltage value during mul...
- Publication number 20060114721
- Publication date Jun 1, 2006
- Massimiliano Frulio
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for managing address bits during buffered program...
- Publication number 20060085622
- Publication date Apr 20, 2006
- Simone Bartoli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Column decoding architecture for flash memories
- Publication number 20060077746
- Publication date Apr 13, 2006
- Stefano Sivero
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for a programming approach for a nonvolatile elec...
- Publication number 20060077714
- Publication date Apr 13, 2006
- Stefano Surico
- G11 - INFORMATION STORAGE
Information Patent Application
Compensated method to implement a high voltage discharge phase afte...
- Publication number 20060062063
- Publication date Mar 23, 2006
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE
Information Patent Application
VARIABLE CHARGE PUMP CIRCUIT WITH DYNAMIC LOAD
- Publication number 20040080360
- Publication date Apr 29, 2004
- Lorenzo Bedarida
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Flash memory architecture with page mode erase using NMOS and PMOS...
- Publication number 20040076037
- Publication date Apr 22, 2004
- Lorenzo Bedarida
- G11 - INFORMATION STORAGE

Simone Bartoli

Person

Patents Grantslast 30 patents

Memory device, memory address decoder, system, and related method f...

Erase techniques and circuits therefor for non-volatile memory devices

Method of programming selection transistors for NAND flash memory

Erase techniques and circuits therefor for non-volatile memory devices

Method and circuit to discharge bit lines after an erase pulse

Memory device in particular extra array configured therein for conf...

Sense amplifier

Compensated current offset in a sensing circuit

Flexible, low cost apparatus and method to introduce and check algo...

Non-volatile memory array architecture with joined word lines

Sense architecture

Implementation of column redundancy for a flash memory with a high...

Method and system for reducing soft-writing in a multi-level flash...

Method and apparatus for discharging a memory cell in a memory devi...

Erase verify method for NAND-type flash memories

Method and system for managing address bits during buffered program...

Method and system for regulating a program voltage value during mul...

Method and system for a programming approach for a nonvolatile elec...

Column decoding architecture for flash memories

Method and system for managing a suspend request in a flash memory

System and method for matching resistance in a non-volatile memory

System for configuring parameters for a flash memory

Method and system for regulating a program voltage value during mul...

Method and system for configuring parameters for flash memory

Compensated method to implement a high voltage discharge phase afte...

System for performing fast testing during flash reference cell setting

Autotesting method of a memory cell matrix, particularly of the non...

Non-volatile memory with functional capability of simultaneous modi...

Non-volatile memory device with burst mode reading and correspondin...

Flash memory architecture with page mode erase using NMOS and PMOS...

Patents Applicationslast 30 patents

MEMORY DEVICE, MEMORY ADDRESS DECODER, SYSTEM, AND RELATED METHOD F...

Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices

METHOD OF PROGRAMMING SELECTION TRANSISTORS FOR NAND FLASH MEMORY

SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHO...

MEMORY DEVICE IN PARTICULAR EXTRA ARRAY CONFIGURED THEREIN FOR CONF...

ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICES

METHOD AND CIRCUIT TO DISCHARGE BIT LINES AFTER AN ERASE PULSE

SENSE AMPLIFIER

NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES

FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGO...

NAND-LIKE MEMORY ARRAY EMPLOYING HIGH-DENSITY NOR-LIKE MEMORY DEVICES

Sense architecture

Compensated current offset in a sensing circuit

ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES

IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH...

System for configuring parameters for a flash memory

Method and system for regulating a program voltage value during mul...

Method and apparatus for discharging a memory cell in a memory devi...

System and method for matching resistance in a non-volatile memory

Method and system for configuring parameters for flash memory

Method and system for managing a suspend request in a flash memory

System for performing fast testing during flash reference cell setting

Method and system for reducing soft-writing in a multi-level flash...

Method and system for regulating a program voltage value during mul...

Method and system for managing address bits during buffered program...

Column decoding architecture for flash memories

Method and system for a programming approach for a nonvolatile elec...

Compensated method to implement a high voltage discharge phase afte...

VARIABLE CHARGE PUMP CIRCUIT WITH DYNAMIC LOAD

Flash memory architecture with page mode erase using NMOS and PMOS...