Siva Venkatraman

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for reconfigurable memory
- Patent number 7,502,977
- Issue date Mar 10, 2009
- Intel Corporation
- Siva Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reconfigurable memory
- Patent number 7,490,260
- Issue date Feb 10, 2009
- Intel Corporation
- Siva Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
IC memory complex with controller for clusters of memory blocks I/O...
- Patent number 7,318,115
- Issue date Jan 8, 2008
- Intel Corporation
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified shared pipeline allowing deactivation of RISC/DSP units for...
- Patent number 7,287,148
- Issue date Oct 23, 2007
- Intel Corporation
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus state keepers
- Patent number 7,233,166
- Issue date Jun 19, 2007
- Intel Corporation
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reconfigurable memory
- Patent number 7,111,190
- Issue date Sep 19, 2006
- Intel Corporation
- Siva Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectively multiplexing memory coupling global bus data bits to na...
- Patent number 6,732,203
- Issue date May 4, 2004
- Intel Corporation
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for reconfigurable memory
- Publication number 20060010335
- Publication date Jan 12, 2006
- Siva Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reconfigurable memory
- Publication number 20050146910
- Publication date Jul 7, 2005
- Siva Venkatraman
- G11 - INFORMATION STORAGE
Information Patent Application
Unified instruction pipeline for power reduction in a digital signa...
- Publication number 20050076194
- Publication date Apr 7, 2005
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory with memory clusters for power reduction in an integrated ci...
- Publication number 20040236896
- Publication date Nov 25, 2004
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for power reduction in a digital signal processor integrate...
- Publication number 20040078612
- Publication date Apr 22, 2004
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power reduction in a digital signal proces...
- Publication number 20040078608
- Publication date Apr 22, 2004
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power reduction in a digital signal proces...
- Publication number 20040039952
- Publication date Feb 26, 2004
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for power reduction in a digital signal proces...
- Publication number 20030056134
- Publication date Mar 20, 2003
- Ruban Kanapathippillai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reconfigurable memory
- Publication number 20020120826
- Publication date Aug 29, 2002
- Siva Venkatraman
- G11 - INFORMATION STORAGE

Siva Venkatraman

Person

Patents Grantslast 30 patents

Method and apparatus for reconfigurable memory

Method and apparatus for reconfigurable memory

IC memory complex with controller for clusters of memory blocks I/O...

Unified shared pipeline allowing deactivation of RISC/DSP units for...

Bus state keepers

Method and apparatus for reconfigurable memory

Selectively multiplexing memory coupling global bus data bits to na...

Patents Applicationslast 30 patents

Method and apparatus for reconfigurable memory

Method and apparatus for reconfigurable memory

Unified instruction pipeline for power reduction in a digital signa...

Memory with memory clusters for power reduction in an integrated ci...

Methods for power reduction in a digital signal processor integrate...

Method and apparatus for power reduction in a digital signal proces...

Method and apparatus for power reduction in a digital signal proces...

Method and apparatus for power reduction in a digital signal proces...

Method and apparatus for reconfigurable memory