Somasunder Kattepura Sreenath

Follow

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Universal serializer architecture
- Patent number 9,465,759
- Issue date Oct 11, 2016
- Texas Instruments Incorporated
- Somasunder Kattepura Sreenath
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 9,065,430
- Issue date Jun 23, 2015
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 8,704,550
- Issue date Apr 22, 2014
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Synchronous clock multiplexing and output-enable
- Patent number 8,054,103
- Issue date Nov 8, 2011
- Texas Instruments Incorporated
- Jayawardan Janardhanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constant margin CMOS biasing circuit
- Patent number 7,522,003
- Issue date Apr 21, 2009
- Texas Instruments Incorporated
- Sumantra Seth
- G05 - CONTROLLING REGULATING
Information Patent Grant
Gate leakage insensitive current mirror circuit
- Patent number 7,332,965
- Issue date Feb 19, 2008
- Texas Instruments Incorporated
- Sumantra Seth
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
Universal Serializer Architecture
- Publication number 20160019174
- Publication date Jan 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Somasunder Kattepura Sreenath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20140247071
- Publication date Sep 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20090140772
- Publication date Jun 4, 2009
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTANT MARGIN CMOS BIASING CIRCUIT
- Publication number 20080150638
- Publication date Jun 26, 2008
- SUMANTRA SETH
- G05 - CONTROLLING REGULATING
Information Patent Application
GATE LEAKAGE INSENSITIVE CURRENT MIRROR CIRCUIT
- Publication number 20070247230
- Publication date Oct 25, 2007
- SUMANTRA SETH
- G05 - CONTROLLING REGULATING