Son H. Tran

Person

Murphy, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 12,204,905
- Issue date Jan 21, 2025
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-dimensional zero padding in a stream of matrix elements
- Patent number 12,118,358
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-dimensional zero padding in a stream of matrix elements
- Patent number 12,045,617
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exposing valid byte lanes as vector predicates to CPU
- Patent number 11,941,399
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 11,907,721
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implied fence on stream open
- Patent number 11,782,718
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting codes for multi-master memory controller
- Patent number 11,768,733
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exposing valid byte lanes as vector predicates to CPU
- Patent number 11,269,638
- Issue date Mar 8, 2022
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting null vectors into a stream of vectors
- Patent number 11,256,508
- Issue date Feb 22, 2022
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-dimensional zero padding in a stream of matrix elements
- Patent number 11,249,759
- Issue date Feb 15, 2022
- Texas Instruments Incorporated
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting codes for multi-master memory controller
- Patent number 11,249,842
- Issue date Feb 15, 2022
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
One-dimensional zero padding in a stream of matrix elements
- Patent number 11,231,929
- Issue date Jan 25, 2022
- Texas Instruments Incorporated
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting predefined pad values into a stream of vectors
- Patent number 11,113,062
- Issue date Sep 7, 2021
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implied fence on stream open
- Patent number 10,963,255
- Issue date Mar 30, 2021
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two address translations from a single table look-aside buffer read
- Patent number 10,901,913
- Issue date Jan 26, 2021
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20250036411
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20240378058
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU
- Publication number 20240231827
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
- Publication number 20240192956
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20240036867
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
- Publication number 20230393933
- Publication date Dec 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU
- Publication number 20220197637
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING NULL VECTORS INTO A STREAM OF VECTORS
- Publication number 20220179652
- Publication date Jun 9, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
- Publication number 20220164252
- Publication date May 26, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20220164188
- Publication date May 26, 2022
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONE-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20220147484
- Publication date May 12, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
- Publication number 20210349716
- Publication date Nov 11, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20210216316
- Publication date Jul 15, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ
- Publication number 20210149820
- Publication date May 20, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER
- Publication number 20200371874
- Publication date Nov 26, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inserting Null Vectors nto a Stream of Vectors
- Publication number 20190278597
- Publication date Sep 12, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
One-Dimensional Zero Padding in a Stream of Matrix Elements
- Publication number 20190278595
- Publication date Sep 12, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Son Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-Dimensioanl Zero Padding in a Stream of Matrix Elements
- Publication number 20190278596
- Publication date Sep 12, 2019
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inserting Predefined Pad Values into a Stream of Vectors
- Publication number 20190278598
- Publication date Sep 12, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20190220276
- Publication date Jul 18, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ
- Publication number 20190188151
- Publication date Jun 20, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU
- Publication number 20190004797
- Publication date Jan 3, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASSIDE BUFFER READ
- Publication number 20170132149
- Publication date May 11, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING

Son H. Tran

Person

Patents Grantslast 30 patents

Inserting predefined pad values into a stream of vectors

One-dimensional zero padding in a stream of matrix elements

Two-dimensional zero padding in a stream of matrix elements

Exposing valid byte lanes as vector predicates to CPU

Inserting predefined pad values into a stream of vectors

Implied fence on stream open

Error correcting codes for multi-master memory controller

Exposing valid byte lanes as vector predicates to CPU

Inserting null vectors into a stream of vectors

Two-dimensional zero padding in a stream of matrix elements

Error correcting codes for multi-master memory controller

One-dimensional zero padding in a stream of matrix elements

Inserting predefined pad values into a stream of vectors

Implied fence on stream open

Two address translations from a single table look-aside buffer read

Patents Applicationslast 30 patents

PADDING IN A STREAM OF MATRIX ELEMENTS

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

IMPLIED FENCE ON STREAM OPEN

ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER

EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU

INSERTING NULL VECTORS INTO A STREAM OF VECTORS

ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

ONE-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

IMPLIED FENCE ON STREAM OPEN

TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ

ERROR CORRECTING CODES FOR MULTI-MASTER MEMORY CONTROLLER

Inserting Null Vectors nto a Stream of Vectors

One-Dimensional Zero Padding in a Stream of Matrix Elements

Two-Dimensioanl Zero Padding in a Stream of Matrix Elements

Inserting Predefined Pad Values into a Stream of Vectors

IMPLIED FENCE ON STREAM OPEN

TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ

EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU

TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASSIDE BUFFER READ