Sonia Singhal

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Santa Clara, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Automatic generation of merged mode constraints for electronic circ...
- Patent number 8,627,262
- Issue date Jan 7, 2014
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic verification of merged mode constraints for electronic ci...
- Patent number 8,607,186
- Issue date Dec 10, 2013
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for rapidly modeling and simulating intra-die...
- Patent number 8,290,761
- Issue date Oct 16, 2012
- Carnegie Mellon University
- Amith Singhee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comparing timing constraints of circuits
- Patent number 8,261,221
- Issue date Sep 4, 2012
- Synopsys, Inc.
- Sonia Singhal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRC...
- Publication number 20110252393
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPARING TIMING CONSTRAINTS OF CIRCUITS
- Publication number 20110252388
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Sonia Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CI...
- Publication number 20110252390
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING