Soon Chieh LIM

Person

Bayan Lepas Pulau Pinang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Method and a system for network-on-chip arbitration
- Patent number 12,199,884
- Issue date Jan 14, 2025
- SKYECHIP SDN BHD
- Yeong Tat Liew
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for transferring configuration, management, debug...
- Patent number 12,149,407
- Issue date Nov 19, 2024
- SKYECHIP SDN BHD
- Soon Chieh Lim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus of receive enable margining in memory interface
- Patent number 12,125,518
- Issue date Oct 22, 2024
- SKYECHIP SDN BHD
- Soon Chieh Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and a method for synchronizing output clock signals acros...
- Patent number 11,509,312
- Issue date Nov 22, 2022
- SKYECHIP SDN BHD
- Chee Hak Teh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory sequencer system and a method of memory sequencing using the...
- Patent number 11,442,878
- Issue date Sep 13, 2022
- SKYECHIP SDN BHD
- Chee Hak Teh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generic physical layer providing a unified architecture for interfa...
- Patent number 11,373,694
- Issue date Jun 28, 2022
- SKYECHIP SDN BHD
- Soon Chieh Lim
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and a method for handling non-continuous data transfer fo...
- Patent number 11,349,691
- Issue date May 31, 2022
- SKYECHIP SDN BHD
- Soon Chieh Lim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
I/O transmitter circuitry for supporting multi-modes serialization
- Patent number 11,349,481
- Issue date May 31, 2022
- SKYECHIP SDN BHD
- Selvakumar Sivarajah
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
NETWORK-ON-CHIP PACKETIZATION AND ROUTING METHOD AND APPARATUS FOR...
- Publication number 20240297846
- Publication date Sep 5, 2024
- SKYECHIP SDN BHD
- Chee Hak TEH
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND A METHOD FOR ALIGNING A PROGRAMMABLE CLOCK OR STROBE
- Publication number 20240192721
- Publication date Jun 13, 2024
- SKYECHIP SDN BHD
- TAT HIN TAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND A SYSTEM FOR NETWORK-ON-CHIP ARBITRATION
- Publication number 20240163223
- Publication date May 16, 2024
- SKYECHIP SDN BHD
- YEONG TAT LIEW
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR TRANSFERRING CONFIGURATION, MANAGEMENT, DEBUG...
- Publication number 20240129183
- Publication date Apr 18, 2024
- SKYECHIP SDN BHD
- Soon Chieh LIM
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD OF DEBUGGING NETWORK-ON-CHIP
- Publication number 20240070039
- Publication date Feb 29, 2024
- SKYECHIP SDN BHD
- Yu Ying ONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS OF RECEIVE ENABLE MARGINING IN MEMORY INTERFACE
- Publication number 20230230628
- Publication date Jul 20, 2023
- SKYECHIP SDN BHD
- Soon Chieh LIM
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER FOR IMPROVING DATA INTEGRITY AND PROVIDING DATA S...
- Publication number 20220253536
- Publication date Aug 11, 2022
- SKYECHIP SDN BHD
- YU YING ONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERIC PHYSICAL LAYER PROVIDING A UNIFIED ARCHITECTURE FOR INTERFA...
- Publication number 20220208240
- Publication date Jun 30, 2022
- SKYECHIP SDN BHD
- Soon Chieh LIM
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SEQUENCER SYSTEM AND A METHOD OF MEMORY SEQUENCING USING THE...
- Publication number 20220164298
- Publication date May 26, 2022
- SKYECHIP SDN BHD
- CHEE HAK TEH
- G01 - MEASURING TESTING

Soon Chieh LIM

Person

Patents Grantslast 30 patents

Method and a system for network-on-chip arbitration

System and method for transferring configuration, management, debug...

Method and apparatus of receive enable margining in memory interface

Apparatus and a method for synchronizing output clock signals acros...

Memory sequencer system and a method of memory sequencing using the...

Generic physical layer providing a unified architecture for interfa...

Apparatus and a method for handling non-continuous data transfer fo...

I/O transmitter circuitry for supporting multi-modes serialization

Patents Applicationslast 30 patents

NETWORK-ON-CHIP PACKETIZATION AND ROUTING METHOD AND APPARATUS FOR...

SYSTEM AND A METHOD FOR ALIGNING A PROGRAMMABLE CLOCK OR STROBE

METHOD AND A SYSTEM FOR NETWORK-ON-CHIP ARBITRATION

SYSTEM AND METHOD FOR TRANSFERRING CONFIGURATION, MANAGEMENT, DEBUG...

METHOD OF DEBUGGING NETWORK-ON-CHIP

METHOD AND APPARATUS OF RECEIVE ENABLE MARGINING IN MEMORY INTERFACE

MEMORY CONTROLLER FOR IMPROVING DATA INTEGRITY AND PROVIDING DATA S...

GENERIC PHYSICAL LAYER PROVIDING A UNIFIED ARCHITECTURE FOR INTERFA...

MEMORY SEQUENCER SYSTEM AND A METHOD OF MEMORY SEQUENCING USING THE...