Sorin Iacobovici

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
In-field system testing
- Patent number 10,859,627
- Issue date Dec 8, 2020
- Intel Corporation
- Sreejit Chakravarty
- G01 - MEASURING TESTING
Information Patent Grant
In-field system test security
- Patent number 10,491,381
- Issue date Nov 26, 2019
- Intel Corporation
- Neel Shah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Consecutive bit error detection and correction
- Patent number 9,654,143
- Issue date May 16, 2017
- Intel Corporation
- Guillem Sole
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Residue based error detection for integer and floating point execut...
- Patent number 9,110,768
- Issue date Aug 18, 2015
- Intel Corporation
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core sparing on multi-core platforms
- Patent number 8,412,981
- Issue date Apr 2, 2013
- Intel Corporation
- Alberto J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saving and restoring architectural state for processor cores
- Patent number 7,996,663
- Issue date Aug 9, 2011
- Intel Corporation
- Paul M. Stillwell, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
End-to-end residue-based protection of an execution pipeline that s...
- Patent number 7,769,795
- Issue date Aug 3, 2010
- Oracle America, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
End-to-end residue based protection of an execution pipeline
- Patent number 7,555,692
- Issue date Jun 30, 2009
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Residue-based error detection for a shift operation
- Patent number 7,543,007
- Issue date Jun 2, 2009
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-stride prefetcher with a recurring prefetch table
- Patent number 7,487,296
- Issue date Feb 3, 2009
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Versatile register file design for a multi-threaded processor utili...
- Patent number 7,418,582
- Issue date Aug 26, 2008
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling register dependencies between instructions specifying diff...
- Patent number 7,340,590
- Issue date Mar 4, 2008
- Sun Microsystems, Inc.
- Rabin Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reducing off-chip cache memory accesses
- Patent number 7,325,101
- Issue date Jan 29, 2008
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector technique for addressing helper instruction groups associate...
- Patent number 7,219,218
- Issue date May 15, 2007
- Sun Microsystems, Inc.
- Chandra M. R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and a system for using same set of registers to handle both...
- Patent number 7,191,316
- Issue date Mar 13, 2007
- Sun Microsystems, Inc.
- Rabin A. Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing a complex instruction for execu...
- Patent number 7,124,284
- Issue date Oct 17, 2006
- Sun Microsystems, Inc.
- Rabin A. Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register window flattening logic for dependency checking among inst...
- Patent number 7,080,237
- Issue date Jul 18, 2006
- Sun Microsystems, Inc.
- Chandra M. R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for handling condition code modifiers in an out-of-order mul...
- Patent number 7,065,635
- Issue date Jun 20, 2006
- Sun Microsystems, Inc.
- Rabin A. Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for protecting a state associated with a memor...
- Patent number 7,043,609
- Issue date May 9, 2006
- Sun Microsystems, Inc.
- Victor Melamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register window fill technique for retirement window having entry s...
- Patent number 7,035,999
- Issue date Apr 25, 2006
- Sun Microsystems, Inc.
- Chandra Thimmanagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register window spill technique for retirement window having entry...
- Patent number 7,024,541
- Issue date Apr 4, 2006
- Sun Microsystems, Inc.
- Chandra Thimmanagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming linked lists using content addressable memory
- Patent number 6,820,086
- Issue date Nov 16, 2004
- Hewlett-Packard Development Company, L.P.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor speed control mechanism using power dissipation esti...
- Patent number 6,704,876
- Issue date Mar 9, 2004
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling data errors in a computer system
- Patent number 6,453,427
- Issue date Sep 17, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pending access queue for providing data to a target register during...
- Patent number 6,185,660
- Issue date Feb 6, 2001
- Hewlett-Packard Company
- Dean A. Mulla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed memory multiprocessor computer system with directory ba...
- Patent number 6,055,610
- Issue date Apr 25, 2000
- Hewlett-Packard Company
- Kenneth K. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming linked lists using content addressable memory
- Patent number 5,995,967
- Issue date Nov 30, 1999
- Hewlett-Packard Company
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conflict cache having cache miscounters for a computer memory system
- Patent number 5,860,095
- Issue date Jan 12, 1999
- Hewlett-Packard Company
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method using a semaphore buffer for semaphore instruc...
- Patent number 5,696,939
- Issue date Dec 9, 1997
- Hewlett-Packard Co.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache arrangement including coalescing buffer queue for non-cacheab...
- Patent number 5,664,148
- Issue date Sep 2, 1997
- Institute for the Development of Emerging Architectures L.L.C.
- Dean Mulla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
In-Field System Testing
- Publication number 20190004112
- Publication date Jan 3, 2019
- Sreejit Chakravarty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IN-FIELD SYSTEM TEST SECURITY
- Publication number 20190007200
- Publication date Jan 3, 2019
- Intel Corporation
- Neel Shah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONSECUTIVE BIT ERROR DETECTION AND CORRECTION
- Publication number 20150370636
- Publication date Dec 24, 2015
- Guillem Sole
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESIDUE BASED ERROR DETECTION FOR INTEGER AND FLOATING POINT EXECUT...
- Publication number 20140188965
- Publication date Jul 3, 2014
- Sorin IACOBOVICI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable provisioning of computer system resources
- Publication number 20100257294
- Publication date Oct 7, 2010
- Greg Regnier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES
- Publication number 20090172369
- Publication date Jul 2, 2009
- Paul M. Stillwell, JR.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Core sparing on multi-core platforms
- Publication number 20080163255
- Publication date Jul 3, 2008
- Alberto J. Munoz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OFFLOADING OPERATIONS FOR MAINTAINING DATA COHERENCE ACROSS A PLURA...
- Publication number 20080065835
- Publication date Mar 13, 2008
- SUN MICROSYSTEMS, INC.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Residue-based error detection for a shift operation
- Publication number 20070043796
- Publication date Feb 22, 2007
- Sun Microsystems, Inc.
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system to handle register window fill and spill
- Publication number 20040215941
- Publication date Oct 28, 2004
- Sun Microsystems, Inc.
- Chandra M.R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to limit register file read ports in an out-of...
- Publication number 20040199749
- Publication date Oct 7, 2004
- Robert Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Helper logic for complex instructions
- Publication number 20040199753
- Publication date Oct 7, 2004
- Sun Microsystems, Inc.
- Chandra M.R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stall technique to facilitate atomicity in processor execution of h...
- Publication number 20040193845
- Publication date Sep 30, 2004
- Sun Microsystems, Inc.
- Chandra M.R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load and/or store queue emptying technique to facilitate atomicity...
- Publication number 20040193844
- Publication date Sep 30, 2004
- Sun Microsystems, Inc.
- Chandra M.R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for handling control transfer instruction couples in out-of-...
- Publication number 20040162972
- Publication date Aug 19, 2004
- Sorin Iacobovici
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to handle instructions that use non-windowed registers in a...
- Publication number 20040153631
- Publication date Aug 5, 2004
- Chandra M.R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for protecting a state associated with a memor...
- Publication number 20040153609
- Publication date Aug 5, 2004
- SUN MICROSYSTEMS, INC.
- Victor Melamed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for determining an early reifetch address of a...
- Publication number 20040148497
- Publication date Jul 29, 2004
- Ali Vahidsafa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for handling a mix of single precision and double precision...
- Publication number 20040148492
- Publication date Jul 29, 2004
- Rabin A. Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to determine readiness of a complex instructio...
- Publication number 20040133432
- Publication date Jul 8, 2004
- Rabin A. Sugumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheme to simplify instruction buffer logic supporting multiple str...
- Publication number 20040128476
- Publication date Jul 1, 2004
- Robert Nuckolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Strand switching algorithm to avoid strand starvation
- Publication number 20040128488
- Publication date Jul 1, 2004
- Chandra M. R. Thimmannagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for early speculative store-load bypass
- Publication number 20040044881
- Publication date Mar 4, 2004
- Sun Microsystems, Inc.
- Robert M. Maier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register window fill technique for retirement window having entry s...
- Publication number 20030229772
- Publication date Dec 11, 2003
- Chandra Thimmanagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register window spill technique for retirement window having entry...
- Publication number 20030229771
- Publication date Dec 11, 2003
- Chandra Thimmanagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register flattening logic
- Publication number 20030221088
- Publication date Nov 27, 2003
- Chandra Thimmanagari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM
- Publication number 20010049798
- Publication date Dec 6, 2001
- NHON T. QUACH
- G06 - COMPUTING CALCULATING COUNTING

Sorin Iacobovici

Person

Patents Grantslast 30 patents

In-field system testing

In-field system test security

Consecutive bit error detection and correction

Residue based error detection for integer and floating point execut...

Core sparing on multi-core platforms

Saving and restoring architectural state for processor cores

End-to-end residue-based protection of an execution pipeline that s...

End-to-end residue based protection of an execution pipeline

Residue-based error detection for a shift operation

Multi-stride prefetcher with a recurring prefetch table

Versatile register file design for a multi-threaded processor utili...

Handling register dependencies between instructions specifying diff...

Techniques for reducing off-chip cache memory accesses

Vector technique for addressing helper instruction groups associate...

Method and a system for using same set of registers to handle both...

Method and apparatus for processing a complex instruction for execu...

Register window flattening logic for dependency checking among inst...

Method for handling condition code modifiers in an out-of-order mul...

Method and apparatus for protecting a state associated with a memor...

Register window fill technique for retirement window having entry s...

Register window spill technique for retirement window having entry...

Forming linked lists using content addressable memory

Microprocessor speed control mechanism using power dissipation esti...

Method and apparatus for handling data errors in a computer system

Pending access queue for providing data to a target register during...

Distributed memory multiprocessor computer system with directory ba...

Forming linked lists using content addressable memory

Conflict cache having cache miscounters for a computer memory system

Apparatus and method using a semaphore buffer for semaphore instruc...

Cache arrangement including coalescing buffer queue for non-cacheab...

Patents Applicationslast 30 patents

In-Field System Testing

IN-FIELD SYSTEM TEST SECURITY

CONSECUTIVE BIT ERROR DETECTION AND CORRECTION

RESIDUE BASED ERROR DETECTION FOR INTEGER AND FLOATING POINT EXECUT...

Configurable provisioning of computer system resources

SAVING AND RESTORING ARCHITECTURAL STATE FOR PROCESSOR CORES

Core sparing on multi-core platforms

OFFLOADING OPERATIONS FOR MAINTAINING DATA COHERENCE ACROSS A PLURA...

Residue-based error detection for a shift operation

Method and system to handle register window fill and spill

Method and apparatus to limit register file read ports in an out-of...

Helper logic for complex instructions

Stall technique to facilitate atomicity in processor execution of h...

Load and/or store queue emptying technique to facilitate atomicity...

Method for handling control transfer instruction couples in out-of-...

Method to handle instructions that use non-windowed registers in a...

Method and apparatus for protecting a state associated with a memor...

Method and apparatus for determining an early reifetch address of a...

Method for handling a mix of single precision and double precision...

Method and apparatus to determine readiness of a complex instructio...

Scheme to simplify instruction buffer logic supporting multiple str...

Strand switching algorithm to avoid strand starvation

Method and system for early speculative store-load bypass

Register window fill technique for retirement window having entry s...

Register window spill technique for retirement window having entry...

Register flattening logic

METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM