Sowmiya Jayachandran

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for exiting low power states in memory devices
- Patent number 11,249,531
- Issue date Feb 15, 2022
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically changing between latency-focused read operation and ban...
- Patent number 11,036,412
- Issue date Jun 15, 2021
- Intel Corporation
- Sahar Khalili
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for exiting low power states in memory devices
- Patent number 10,437,307
- Issue date Oct 8, 2019
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing disturbance induced errors
- Patent number 10,153,015
- Issue date Dec 11, 2018
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for entry to a lower power state for a memory device
- Patent number 9,916,104
- Issue date Mar 13, 2018
- Intel Corporation
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for entry to a lower power state for a memory device
- Patent number 9,818,458
- Issue date Nov 14, 2017
- Intel Corporation
- Sowmiya Jayachandran
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing disturbance induced errors
- Patent number 9,792,963
- Issue date Oct 17, 2017
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for exiting low power states in memory devices
- Patent number 9,778,723
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for facilitating power and performance management of non-...
- Patent number 9,417,684
- Issue date Aug 16, 2016
- Intel Corporation
- Simon D. Ramage
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Managing disturbance induced errors
- Patent number 9,202,547
- Issue date Dec 1, 2015
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
ECC functional block placement in a multi-channel mass storage device
- Patent number 8,001,444
- Issue date Aug 16, 2011
- Intel Corporation
- Andrew Vogan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DYNAMICALLY CHANGING BETWEEN LATENCY-FOCUSED READ OPERATION AND BAN...
- Publication number 20200034061
- Publication date Jan 30, 2020
- Intel Corporation
- Sahar KHALILI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES
- Publication number 20200019227
- Publication date Jan 16, 2020
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NVRAM MEMORY MODULE WITH HARD WRITE THROTTLE DOWN
- Publication number 20190278503
- Publication date Sep 12, 2019
- Intel Corporation
- Sowmiya JAYACHANDRAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20180068695
- Publication date Mar 8, 2018
- Intel Corporation
- Prashant S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES
- Publication number 20170364135
- Publication date Dec 21, 2017
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES
- Publication number 20170185136
- Publication date Jun 29, 2017
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE
- Publication number 20170115916
- Publication date Apr 27, 2017
- Intel Corporation
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20160189757
- Publication date Jun 30, 2016
- PRASHANT S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20140281203
- Publication date Sep 18, 2014
- PRASHANT S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE
- Publication number 20090172213
- Publication date Jul 2, 2009
- Sowmiya Jayachandran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ECC FUNCTIONAL BLOCK PLACEMENT IN A MULTI-CHANNEL MASS STORAGE DEVICE
- Publication number 20090044078
- Publication date Feb 12, 2009
- Andrew Vogan
- G06 - COMPUTING CALCULATING COUNTING

Sowmiya Jayachandran

Person

Patents Grantslast 30 patents

Apparatuses and methods for exiting low power states in memory devices

Dynamically changing between latency-focused read operation and ban...

Apparatuses and methods for exiting low power states in memory devices

Managing disturbance induced errors

Techniques for entry to a lower power state for a memory device

Techniques for entry to a lower power state for a memory device

Managing disturbance induced errors

Apparatuses and methods for exiting low power states in memory devices

Mechanism for facilitating power and performance management of non-...

Managing disturbance induced errors

ECC functional block placement in a multi-channel mass storage device

Patents Applicationslast 30 patents

DYNAMICALLY CHANGING BETWEEN LATENCY-FOCUSED READ OPERATION AND BAN...

APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES

NVRAM MEMORY MODULE WITH HARD WRITE THROTTLE DOWN

MANAGING DISTURBANCE INDUCED ERRORS

APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES

APPARATUSES AND METHODS FOR EXITING LOW POWER STATES IN MEMORY DEVICES

TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE

MANAGING DISTURBANCE INDUCED ERRORS

MANAGING DISTURBANCE INDUCED ERRORS

COMMAND COMPLETION DETECTION IN A MASS STORAGE DEVICE

ECC FUNCTIONAL BLOCK PLACEMENT IN A MULTI-CHANNEL MASS STORAGE DEVICE