SREENIVAS MANDAVA

Person

LOS ALTOS, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for memory chip row hammer threat backpressure...
- Patent number 12,347,507
- Issue date Jul 1, 2025
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Deferred ECC (error checking and correction) memory initialization...
- Patent number 12,321,622
- Issue date Jun 3, 2025
- Intel Corporation
- Sreenivas Mandava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive error correction to improve system memory reliability, ava...
- Patent number 12,235,720
- Issue date Feb 25, 2025
- Intel Corporation
- Rajat Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature-based runtime variability in victim address selection f...
- Patent number 12,099,388
- Issue date Sep 24, 2024
- Intel Corporation
- Sreenivas Mandava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot up memory controller
- Patent number 10,552,643
- Issue date Feb 4, 2020
- Intel Corporation
- John V. Lovelace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for system physical address to memory module a...
- Patent number 10,162,761
- Issue date Dec 25, 2018
- Intel Corporation
- Ashok Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for probabilistic dynamic random access memory row repair
- Patent number 10,102,886
- Issue date Oct 16, 2018
- Intel Corporation
- John H. Crawford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 10,042,562
- Issue date Aug 7, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for determining victim row addresses in a volatile memory
- Patent number 9,824,754
- Issue date Nov 21, 2017
- Intel Corporation
- Sreenivas Mandava
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 9,747,041
- Issue date Aug 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for probabilistic dynamic random access memory row repair
- Patent number 9,449,671
- Issue date Sep 20, 2016
- Intel Corporation
- John H. Crawford
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for determining victim row addresses in a volatile memory
- Patent number 9,269,436
- Issue date Feb 23, 2016
- Intel Corporation
- Sreenivas Mandava
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...
- Publication number 20240061741
- Publication date Feb 22, 2024
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TRANSACTION QUEUE BYPASS BASED ON CONFIGURABLE ADDRESS AND B...
- Publication number 20220179797
- Publication date Jun 9, 2022
- Intel Corporation
- Jeffrey C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS GENERATION FOR ADAPTIVE DOUBLE DEVICE DATA CORRECTION SPARING
- Publication number 20220108764
- Publication date Apr 7, 2022
- Intel Corporation
- Jing LING
- G11 - INFORMATION STORAGE
Information Patent Application
DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY
- Publication number 20220091764
- Publication date Mar 24, 2022
- Intel Corporation
- Sreenivas MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFERRED ECC (ERROR CHECKING AND CORRECTION) MEMORY INITIALIZATION...
- Publication number 20210382640
- Publication date Dec 9, 2021
- Intel Corporation
- Sreenivas MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA SCRAMBLER TO MITIGATE ROW HAMMER CORRUPTION
- Publication number 20210382638
- Publication date Dec 9, 2021
- Intel Corporation
- Ronald ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...
- Publication number 20210264999
- Publication date Aug 26, 2021
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE-BASED RUNTIME VARIABILITY IN VICTIM ADDRESS SELECTION F...
- Publication number 20210109577
- Publication date Apr 15, 2021
- Intel Corporation
- Sreenivas MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR SYSTEM PHYSICAL ADDRESS TO MEMORY MODULE A...
- Publication number 20180276137
- Publication date Sep 27, 2018
- ASHOK RAJ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT UP MEMORY CONTROLLER
- Publication number 20180181336
- Publication date Jun 28, 2018
- Intel Corporation
- John V. LOVELACE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20180004433
- Publication date Jan 4, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20170185315
- Publication date Jun 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Probabilistic Dynamic Random Access Memory Row Repair
- Publication number 20170103795
- Publication date Apr 13, 2017
- Intel Corporation
- John H. Crawford
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for Determining Victim Row Addresses in a Volatile Memory
- Publication number 20160224262
- Publication date Aug 4, 2016
- Intel Corporation
- SREENIVAS MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Probabilistic Dynamic Random Access Memory Row Repair
- Publication number 20140281206
- Publication date Sep 18, 2014
- John H. Crawford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for Determining Victim Row Addresses in a Volatile Memory
- Publication number 20140281207
- Publication date Sep 18, 2014
- Sreenivas Mandava
- G06 - COMPUTING CALCULATING COUNTING

SREENIVAS MANDAVA

Person

Patents Grantslast 30 patents

Method and apparatus for memory chip row hammer threat backpressure...

Deferred ECC (error checking and correction) memory initialization...

Adaptive error correction to improve system memory reliability, ava...

Temperature-based runtime variability in victim address selection f...

Fast boot up memory controller

Apparatus and method for system physical address to memory module a...

Techniques for probabilistic dynamic random access memory row repair

Apparatus and method for a non-power-of-2 size cache in a first lev...

Techniques for determining victim row addresses in a volatile memory

Apparatus and method for a non-power-of-2 size cache in a first lev...

Techniques for probabilistic dynamic random access memory row repair

Techniques for determining victim row addresses in a volatile memory

Patents Applicationslast 30 patents

ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...

MEMORY TRANSACTION QUEUE BYPASS BASED ON CONFIGURABLE ADDRESS AND B...

ADDRESS GENERATION FOR ADAPTIVE DOUBLE DEVICE DATA CORRECTION SPARING

DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY

DEFERRED ECC (ERROR CHECKING AND CORRECTION) MEMORY INITIALIZATION...

DATA SCRAMBLER TO MITIGATE ROW HAMMER CORRUPTION

METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...

TEMPERATURE-BASED RUNTIME VARIABILITY IN VICTIM ADDRESS SELECTION F...

APPARATUS AND METHOD FOR SYSTEM PHYSICAL ADDRESS TO MEMORY MODULE A...

FAST BOOT UP MEMORY CONTROLLER

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

Techniques for Probabilistic Dynamic Random Access Memory Row Repair

Techniques for Determining Victim Row Addresses in a Volatile Memory

Techniques for Probabilistic Dynamic Random Access Memory Row Repair

Techniques for Determining Victim Row Addresses in a Volatile Memory